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| pci 6254 (hb6) dual mode universal pci-to-pci bridge dat a book
pci 6254 (hb6) dual mode universal pci-to-pci bridge dat a book versi on 2.1 december 2003 web s ite : http://www.pl x t ech.co m technic a l support: http://www.pl xtech.co m/su pport phone: 408 77 4-9 0 6 0 800 75 9-3 7 3 5 fax: 408 77 4-2 1 6 9 ? 2003 plx technology, inc. all rights reserved. plx technology, inc. retains the right to m a ke changes to this product at any tim e , without notice. p r oducts m a y have m i nor variations to this publication, known as errata. plx assum e s no liability whatsoever, including infr ingem e nt of a ny patent or copyr ight, for sale and use of plx products. plx technology and the plx logo are registered tradem arks of plx te chnology, inc. other brands and nam e s are property of their respective owners. this device is not designed, intended, authoriz ed, or w a rr anted to be suitable for use in medical, life-support applications, devices or systems or other cr itical applications. plx part num b er: pci 6254-ab66bc; for m er hint part num b er: hb6 order num b er: 6254-s i l-db-p1-2.0 printed in the usa, may 2003 pci 6254 dual-mode universal pci-to-pci bridge adaptive high performance asynchronous 66mhz 64-bit pci-to-pc i bridge for servers, storage, telecommunication, networking and embedded applic ations plx?s late st pci 625 4 6 4 -bit pci-to -pci bridg e i s d e s ign ed fo r hi g h pe rform a n c e, high availa bility appli c ati ons in bus expan sio n s, p r og ram m able data transfe r rate control, fre que ncy conve r si o n s from s l ower pci to fas t er pci or from faste r pci to slowe r pci buses, addre s s re mappi n g , hig h availability hot swap e nablin g and universal system -to-sy stem bri dgin g . pci 6254 has sop h isti ca ted b u ffer manag eme n t and buffer config uratio n options desi gne d to provide custo m izabl e pe rfo r man c e o p timization. ? pci local bus s p ecif i cation rev 2.3 support ? high speed pci buffer supports 3.3v signaling with 5v input sign al toleran ce ? cpci hot swap specification picmg 2.1 r2.0 with pi = 1 support ? device hiding support eli minates mid-tr ansaction extra c tion probl e m s ? programmable 32 bit to 64 bit access conversion. ? programmable address translation to second ar y bus ? flow-through 0 wait state burst up to 4k by tes for optim al large vo lum e dat a transf er ? supports up to 4 simultaneous posted write transac tions and 4 sim u ltane ous delay e d tr ansactions in e ach dire ctio n ? provides 1k b y tes of buff e ring 256 b y te upstream posted write b u ffer 256 b y te downstream posted write buffer 256 b y te upstream read d a ta buff e r 256 b y te downstream read d a ta b u ffer ? programmable prefetch amount of up to 256 b y tes for ma xi mum re a d pe rforma n c e opt imi z a t i on ? supports out of order delay e d transactions ? support secondar y port pci priv ate memor y space ? option to elimin ates possible dead lock on pci-vme bridges befor e o r behind pci 62 54 ? s e rial eep rom loadab le an d program m a ble p c i read only register config urations. ? extern al arbiter or programmable arb itration for 9 bus masters on seco ndar y in terf ace s upport ? 10 secondar y clock outputs with pin controlled enable and ind i vidual m a skable control ? pci mobile design guide a nd power managemen t d3 cold wakeup capable with pme# support ? 16 gpio pins with output co ntrol and 8 are with power up status latch capabilities ? enhanced addres s decoding support 32-bit i/o address rang e 32-bit memor y - m apped i/o addr ess range isa aware mode for legacy support in th e first 64kb of i/o add r ess range vga addressing and p a lette snoo ping support ? provides an ieee standard 1149 .1 jtag interface for boundar y scan test ? asy n chronous design supports standard 66mhz to 33mhz and faster secondar y port speed su ch as 33mhz to 66mh z conv ersion ? pci 6254 package ball lay out is super set of plx pci 6154 and intel 21154 when op erating in trans p arent mode ? industr y stand a rd 31mm x 31 mm 365-ball pbga packag e pci 6254 non-transparent and universal mode features ? programmable transparent, non- transparen t or universal mode operation ? jumper less switching b e tween s y stem and pe r i p h eral slot applications in cpci ? programmable primar y or secon d ar y port s y stem boot up pr iority . ? sem a phore ba ck ed cross-bridge configuration s p ace a ccess ? powerful m u lti-s ource (di r ect en coded, door b e l l , pci reset , ext e r n al p i n) progr am m a ble in terrup t s ? message interru pt support ? optional power up 16m memor y space claim to avoid in itially r e tr y or in itially n o t respond r e qu irement ? behave as a memory mapped pci device ? primar y and secondar y po rt controllable gpios ? power-good input ? availab l e primar y and secondar y power status inputs for port po wer detection ? independen t primar y and se con d ar y port r e set inputs ? configurable primar y and secon d ar y reset outp uts ? stick y user reg i sters im m une to pci resets ? supporting up to 9 second ar y pc i master d e vices pci 6254 d a ta bo o k v 2 .1 ? 2003 plx technology , inc. a ll rights reser v e d. 5 history r e v d a t e descripti o n e n g c h k mk t c h k r e v 0. 1 7/ 7/ 0 1 fi rst m a r k et i n g rel ease o f pc i 62 5 4 dat a b o ok r e v 0. 2 7/ 2 6 / 0 1 seco nd m a r k et i ng rel ease of pc i 62 5 4 dat a bo o k - c o rrected s o me typing m i stakes. r e v 0. 3 8/ 2 7 / 0 1 up dat e d s p eci f i cat i ons x c l kr u n pi ns can be l e ft u n c o n n ected in trans p are n t mode if clkrun m echanism is not e n able d by s o ft ware x r e m ove p r i v at e m e m o ry descri pt i o ns fr om no n- tra n s p are n t m o de section. privat e m e m o ry is only for tra n s p arent m ode . x corrected typi ng m i stakes. r e v 0. 4 9/ 2 7 / 0 1 ad de d pi n l o ca t i on l i s t an d c o rrect ed t y pi n g m i st akes x add p i n list sorted b y lo cation an d n a m e x c l ari f y gp io a n d cl oc k c ont r o l re gi st ers des c ri pt i o ns x clarified reset d e scrip tion i n th e reset ch apter x r e vi si on c o de cha nge d t o 04 h r e v 0. 9 10/ 11/ 01 pre- p r o d u ct i o n rel ease x ad de d po we r m a nagem e nt d 3 - d 0 res e t des c ri pt i o n x mo re d e tailed eerpom op tio n d e scrip tion x a d d n e w ch ap t e r ab ou t pc i 62 54 u s ag e r e v 0. 91 11/ 5/ 0 1 c o r r ect ed e e p r om c l oc k re gi st er descri pt i on corrected t a bl e refe re nces r e v 0. 92 12/ 4/ 0 1 x co rrectio n s in reset ch ap te r: pw r g d does not ca use p_r s t o ut# a n d s _ r s t o u t # t o go act i v e an d doe s not reset t h e en tire ch ip ; software ch i p reset d o e s not cau s e io sign als to g o three-state and causes eepr o m lo ad only in non-t r ans p a r ent mo d e ; s_ rstin# i n pu t is not u s ed in t r an s p a r en t mod e ; s_ clkstb l o w will not cau s e sec ond ary p o rt in tern al reset in non - tran sp aren t mod e ; pci 6 254 n eeds 5 1 2 clo c k t o i n itialize th e bri dge f unct i on s aft e r any rese t . r e v 0. 93 1/ 8/ 0 2 x ad de d descri pt i on a b out l_ s t ata n d ejec t. r e v 1. 0 1/ 1 8 / 0 2 x ma j o r mo d i f i ca tio n to th e res e t ch a p ter ab ou t n on- t r ans p a r en t mode reset m echanism s . t h e followi ng are major the c h a n ges: - non - tran sp aren t mod e p_ rstin# will also reset seco nd ary p o rt r e g i ster s at 0-3f h. - no n- tra n s p are n t m o de s_rs tin # o n ly rese ts seco nda ry p o rt state m achine, not re gisters . - pw rgd i n itiated eepr o m au to lo ad i n non - tran sp aren t mo d e can only be e f fective if the pwrgd rising ed g e is align e d with or com e after p_rstin# rising edge . eepr o m chapter is also up dat e d t o des c ri be t h e r e q u i r em ent . - co rrected descrip tion o n power man a g e men t in itiated r e set wh ich will not cau se p_ rs tout# and s_ rstout#. x updated s p ecification on re gi ster d8h, bit 4. t h e c o rrect read b ack d a ta is inv e rted wh ile the write d a ta is n o t . pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 6 r e v d a t e descripti o n e n g c h k mk t c h k r e v 1. 1 3/ 7/ 0 2 x ad de d m o re d e scri pt i o ns a b o u t b a r m a sks i n n o n-t r a n sp arent m ode. x up dat e d reset pi n st at e desc ri pt i o n s , a d ded p o we r up a n d r e set pi n st at e t a bl e an d adde d reset t o f i rst cy cl e l a t e ncy descri pt i o n sect i on x in tra n s p are n t m ode , rem ove d p r i v at e de vi ce su p p o r t an d sup p o rt s only private m e m o ry. signal nam e i s chan g e d fr om pr v_ dev t o prv_mem . x eeprom l o catio n 2 c h b it 1 an d 3 d e fin ition s were swapped an d are no w c o rrect ed . eepr o m c o nt r o l re gi st ers defi ni t i ons f o r eepr o m clock spee d is corrected. x corrected m i nor typing m i sta k es r e v 1. 2 6/ 3/ 0 2 x r e m ove t r ans p are n t m o de p r i v at e m e m o ry ena b l e pi n i n put feature . x ad de d descri pt i on a b out act i v e xb _m em w i nd ow set u p i n no n- transp aren t m o d e will b e deco d e d as ad d ition a l priv ate m e m o ry in tr ansp ar en t m o d e if sof t w a r e is u s ed t o sw itch th e pci 6254 f r o m n o n - t r an sp a r en t mo d e to t r an s p a r en t mod e . x adde d prim ary port acces s only for re gister e6h errata des c ription f o r h o t s w ap co n t r o l in u n iv er s a l non - tr an sp a r en t mod e . x ad de d e rrat a d e scri pt i o n fo r uni v ersal n o n - tra n s p are n t m ode eeprom l o aded device id. x ad de d m o re d e t a i l e d desc ri pt i on f o r fo rce 3 2 / 6 4 bi t c o nve rsi o n co n t ro l op tio n. x ad de d f o r ce 6 4 bi t co nt r o l fe at ures x ad de d jt a g i n p u t si gnal s re qui rem e nt for ext e r n al p u l l - u p or p u l l - low resistors. x up dat e d tra n s p are n t m o de t r ansl at i o n r e gi st er u s e descri pt i o n . r e v 1. 3 9/ 1 7 / 0 2 x ad de d r e v a b feat u r es desc ri pt i o ns a n d hi ghl i g ht s r e v a a onl y feature s . x ad de d m o re d e scri pt i o n fo r r e gi st er d9 h b i t 3. x correct desc ription m i stakes ab ou t reg i ster 96 h and 97 h. x ad de d new fea t ure desc ri pt i o n fo r xb _m e m co nt rol x ad de d ca ut i o n s f o r use o f fl o w t h r o ug h o p t i m i zat i ons x ad de d p o wer up an d reset st at e t a bl e r e v 1. 31 10/ 2/ 0 2 x c o r r ect ed s_r s ti n# pi n des c ri pt i o n. it i s o n l y use d fo r n o n - transpa r ent m ode x gpio 15 :8 i n tern al pu ll do wn clai m is re m o ved x c l ari f i e d t r an s l at i on ad d r ess r e gi st ers a n d a d dress t r a n sl at i o n mechanism . r e v 2. 0 5/ 2 3 / 0 3 thi s rel ease re fl ect s pl x part n u m b eri n g . x up dat e d r e gi s t er de h, bi t s 1 5 - 1 1 x ad de d t h ree n o t e s t o t a bl e i n sect i on 1 4 . 5 , f r eq ue ncy di vi si on op tion s r e v 2. 1 12/ 10/ 03 r e m ove re fer e nce t o heat si nk i n sect i o n 2 6 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 7 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 8 contents history ........................................................................................................................ ........................................... 6 1 register index ............................................................................................................... ............................. 15 2 ordering in formation ......................................................................................................... ................... 16 3 using t h e pci 6254 ........................................................................................................... ........................... 17 3.1 t ransparent m ode a pplicatio n .............................................................................................................. 17 3.2 s tandar d n on ?t ransparent a pplica t i o n .............................................................................................. 18 3.3 u niversal b ridgi n g a ppli c ation .............................................................................................................. 19 3.3.1 uni v ersal m o de clk, rst # , req# , gnt# and sysen# signal connections .................................. 20 3.4 s y mme trical n on ?t ransparent a pplicatio n ......................................................................................... 21 4 pin diagram .................................................................................................................. ................................ 22 5 signal de finition ............................................................................................................ ........................... 23 5.1 p rimar y b us i nter face s ig n a l s ............................................................................................................... 23 5.2 p rimar y b us i nter face 64- bit e xtension s ignals .................................................................................. 25 5.3 s eco n dary b us i nte r face s ignals .......................................................................................................... 26 5.4 s eco n dary b us i nte r face 64- bit e xtensio n s ig n a l s ............................................................................. 28 5.5 c lock r elated s igna ls ............................................................................................................................ 29 5.6 r eset s ignal s ............................................................................................................................... ............ 30 5.7 h ot s wap s ig n a l s ............................................................................................................................... ...... 31 5.8 m iscellaneous s igna ls ............................................................................................................................ 31 5.9 m ultiplexed t ransparent and n on -t ransparent m ode s igna ls ......................................................... 33 5.10 jtag/b ound ar y s can i nter f a c e s ig n a l s ............................................................................................... 34 5.11 p ow e r s ig n a l s ............................................................................................................................... ........... 34 5.12 p in a ssignme nt s orte d b y l ocat io n ....................................................................................................... 35 5.13 p in a ssignme nt s orte d b y p in n ame ....................................................................................................... 37 6 configuratio n regis t ers ...................................................................................................... ................ 39 6.1 c onfi gura t i on s pace m ap ? t ransparent m ode ................................................................................... 39 6.2 e xtended r eg i s t e r m ap ........................................................................................................................... 40 6.2.1 address trans la tion regis t er map ......................................................................................... ............ 41 6.3 t ransparent m ode c on fi gura tio n r eg ister d escription .................................................................... 42 6.3.1 pci standard config uration r egi sters ..................................................................................... .......... 42 6.3.2 prefetc h c ont rol regis t ers ............................................................................................... .................. 54 6.3.3 priv at e mem o ry ........................................................................................................... ....................... 65 6.3.4 gpio regis t ers ........................................................................................................... ....................... 66 6.3.5 extended registers ....................................................................................................... ..................... 68 6.3.6 power managem ent and hot swap re gisters .................................................................................. . 69 6.3.7 vpd r egis t ers ............................................................................................................ ........................ 72 7 pci bus op eration ............................................................................................................ ......................... 73 7.1 pci t ransac tions ............................................................................................................................... ...... 73 7.2 s ingle a ddress p hase ............................................................................................................................. 73 7.3 d ual a ddres s p hase ............................................................................................................................... . 73 7.4 d evice s elect (devsel#) g eneration ................................................................................................... 74 7.5 d ata p hase ............................................................................................................................... ................. 74 7.5.1 pos t ed write trans a c t ions ................................................................................................ ................. 74 7.5.2 mem o ry writ e and in validate tran sacti ons ................................................................................. ....... 75 7.5.3 delay e d writ e trans a c t ions ............................................................................................... ................ 75 7.5.4 write t r ansacti on address boundaries ..................................................................................... ......... 76 7.5.5 buffering multiple write transac tions .................................................................................... ............ 76 7.5.6 read tr ansac t ions ........................................................................................................ ..................... 77 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 9 7.5.7 prefetc h able re ad transac t ions ........................................................................................... ............. 77 7.5.8 nonprefet c habl e read trans a c t ions ........................................................................................ .......... 77 7.5.9 read prefetch address boundaries ......................................................................................... .......... 77 7.5.10 delay e d read reques ts ................................................................................................... ................. 78 7.5.11 delay e d read co mpletion wi th target ..................................................................................... ......... 78 7.5.12 delay e d read comp letion on init iator bus ................................................................................ ........ 78 7.5.13 configuration trans a c t ions .............................................................................................. .................. 79 7.5.14 type-0 a ccess to pci 6254 ............................................................................................... ................. 80 7.5.15 ty pe-1 to type-0 trans l ation ............................................................................................ ................. 80 7.5.16 ty pe-1 to type-1 forwarding ............................................................................................. ................ 81 7.5.17 spec ial cyc l es .......................................................................................................... .......................... 82 7.6 t ransacti on t erminati o n ........................................................................................................................ 82 7.6.1 mas t er termination initiated by pci 6254 ................................................................................. ......... 83 7.6.2 master abort recei v ed by pci 6254 ........................................................................................ .......... 83 7.6.3 target terminati on received by pci 6254 .................................................................................. ...... 84 7.6.3.1 delay e d write t a r get t e rminati on resp onse .............................................................................. .................. 84 7.6.3.2 posted write tar get t e rminati on resp onse ............................................................................... ................... 84 7.6.3.3 delay e d read t a r get t e rminati on resp onse ............................................................................... ................. 85 7.6.4 target termination initiated by pci 6254 ................................................................................. ......... 86 7.6.4.1 t a r get retry ........................................................................................................... ........................................ 86 7.6.4.2 t a rget disconnec ted .................................................................................................... .................................. 87 7.6.4.3 t a r get-abor t ........................................................................................................... ........................................ 87 8 address de codi ng ............................................................................................................. ....................... 88 8.1 a ddress r ang e s ............................................................................................................................... ........ 88 8.2 i/o a ddress d eco d ing .............................................................................................................................. 8 8 8.2.1 i/o base and lim i t address r egi sters ..................................................................................... .......... 88 8.3 isa m ode ............................................................................................................................... .................... 89 8.4 m emo r y a ddress d eco d i n g ..................................................................................................................... 90 8.4.1 mem o ry-mapped i/o base and lim i t address regi ster s ................................................................... 90 8.4.2 prefetchable mem o ry base and lim i t address regist er s .................................................................. 91 8.5 vga s upport ............................................................................................................................... ............. 92 8.5.1 vg a mode ................................................................................................................. ......................... 92 8.5.2 vga snoop m ode ........................................................................................................... ................... 92 8.6 p rivate d evice s upport ........................................................................................................................... 93 8.7 a ddress t ra nslation ............................................................................................................................... 93 8.7.1 bas e address regis t ers ................................................................................................... .................. 93 8.7.2 configuration addre s s trans l ation operation .............................................................................. ...... 93 9 trans acti o n orde ri ng ......................................................................................................... .................. 95 9.1 t ransacti on o rdering ............................................................................................................................. 95 9.1.1 trans a c t ions govern ed by ordering rules .................................................................................. ...... 95 9.1.2 general orde ring gui delines .............................................................................................. ................ 95 9.1.3 orderi ng rules ........................................................................................................... ........................ 96 9.1.4 data sy nc hroniz ation ..................................................................................................... .................... 97 10 er r o r hand ling .............................................................................................................. ....................... 98 10.1 a ddress p arity e rr ors ........................................................................................................................... 98 10.2 d ata p arity e rrors ............................................................................................................................... .. 99 10.2.1 configuration write trans a c t ions to conf i guration spac e ................................................................. 99 10.2.2 read transac t ions ....................................................................................................... ...................... 99 10.2.3 delay e d writ e trans a c t ions .............................................................................................. ............... 100 10.2.4 pos t ed write trans a c t ions ............................................................................................... ................ 101 10.3 d ata p arity e rror r eporting s umma r y .............................................................................................. 102 10.4 s ys t e m e rr or (serr# ) r epo rti n g ....................................................................................................... 106 11 exclusi ve access ............................................................................................................ .................... 107 11.1 c oncurre nt l ock s ............................................................................................................................... .. 107 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 10 11.2 a cqui rin g e x c lusive a cce ss a cross pci 6254 .................................................................................... 107 11.3 e ndin g e xcl u sive a ccess ...................................................................................................................... 108 12 pci bus arbitration ......................................................................................................... ................... 109 12.1 p rimar y pci b us a rbit rat i on ................................................................................................................ 109 12.2 s eco n dary pci b us a rbit ration ........................................................................................................... 109 12.2.1 sec o ndary b u s arbit r ation us ing the inter nal arbiter.................................................................... ... 109 12.2.1 . 1 rotating priori t y schem e ............................................................................................................................... . 110 12.2.1 . 2 fixed priority s c heme ............................................................................................................................... ..... 111 12.2.2 sec o ndary b u s arbit r ation us ing an ex ter nal arbiter ..................................................................... .. 111 12.2.3 internal arbi t r ation park ing ............................................................................................ ................... 111 13 general p urpo se i/o interface ............................................................................................... ...... 112 13.1 gpio c ontr ol r eg iste rs ...................................................................................................................... 113 14 clocks ...................................................................................................................... ............................... 114 14.1 p rimar y and s eco n dary c lock i npu t s .................................................................................................. 114 14.2 s eco n dary c lock o utpu ts .................................................................................................................... 114 14.3 d isabling u nused s eco n dary c lock o utputs ..................................................................................... 114 14.3.1 sec o ndary clock control ................................................................................................. ................. 115 14.3.2 forc e s_clk [ 9:0] to low ................................................................................................. ............... 115 14.4 u sing an e xternal c lock s our c e ......................................................................................................... 116 14.5 f r e q u ency d ivision o pti o ns .................................................................................................................. 116 14.6 r unning s e c ondar y p ort f aster than p rimar y p or t ......................................................................... 116 14.7 u niversal m ode c lock b ehavio r .......................................................................................................... 116 15 frequency operati o n ......................................................................................................... .............. 117 15.1 66-m h z o peration ............................................................................................................................... ... 117 16 reset ....................................................................................................................... ................................. 118 16.1 p ow e r g oo d r eset ............................................................................................................................... . 118 16.1.1 pwrgd and output signal s ................................................................................................ ............ 118 16.2 p rimar y r eset i npu t ............................................................................................................................... 119 16.3 p rimar y r eset o utput ........................................................................................................................... 119 16.4 s eco n dary r eset i nput ......................................................................................................................... 120 16.4.1 uni v ersal m o de se condary re set input .................................................................................... ....... 120 16.5 s eco n dary r eset o utput ...................................................................................................................... 120 16.6 s o f tware c hip r eset ............................................................................................................................. 12 1 16.7 p ow e r m ana g ement i n ternal r eset ..................................................................................................... 121 16.8 r eset to f ir st c yc l e a ccess l atency .................................................................................................. 121 16.9 r eset i nputs t able ............................................................................................................................... .. 122 16.10 p ow e r u p and r eset p in s tate t able ............................................................................................... 123 16.10.1 pci 6254 re v aa power up and reset pin state table ............................................................. 125 17 bri dge be havior ............................................................................................................. ..................... 127 17.1 a bno r ma l t erminati o n (i ni tiated b y b rid g e m aster ) ........................................................................... 127 17.1.1 mas t er abort ............................................................................................................ ......................... 127 17.2 p arity and e rror r epo rting ................................................................................................................. 127 17.2.1 reporting parity errors ................................................................................................. .................... 128 17.3 s eco n dary i d sel m apping .................................................................................................................... 128 17.4 32- bit to 64- bit c yc l e c onversio n ........................................................................................................ 128 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 11 18 flow through optimization ................................................................................................... ......... 129 18.1 c autio n s with n on -o ptimized pci m as ter d evices ............................................................................. 129 18.2 r ead c yc l e o ptimizati o n ....................................................................................................................... 129 18.2.1 prim ary/secondary in itial prefet ch count ................................................................................ ........ 130 18.2.2 prim ary/secondary incr em ental prefet ch count ............................................................................ .. 130 18.2.3 prim ary/secondary ma xim u m prefet ch count ................................................................................ . 130 18.3 r ead p refet ch b ounda ri es ................................................................................................................... 130 19 non-trans p are nt mode ........................................................................................................ ............ 131 19.1 n on -t ransparent m ode c onfi gura t i on s pace m ap ............................................................................ 131 19.1.1 configuration 80h-f f h, s hadow and ext ended regist er s ............................................................... 132 19.1.1 . 1 configuration 8 0h-ffh register s ..................................................................................................................... 132 19.1.1 . 2 extend ed reg i s t er m a p ............................................................................................................................... ... 134 19.1.1 . 3 primar y conf igu r ation shadow r e gisters ......................................................................................................... 135 19.2 n on -t ransparent m ode p rimar y c on figu ra ti on r eg isters d escripti o n ......................................... 136 19.2.1 pci standard config uration r egi sters .................................................................................... ......... 136 19.2.2 subsystem vendor id and subs ystem id .................................................................................... .... 140 19.2.3 secondary p o rt standard pci c onfiguration regi sters sh adow ..................................................... 141 19.2.3 . 1 p r efetch control regis t ers .............................................................................................................................. 1 47 19.2.4 cross bridge configurati on ac c e ss cont rol regis t ers..................................................................... 153 19.2.5 gpio regis t ers .......................................................................................................... ...................... 158 19.2.6 direc t mes s age interrupt regis t ers ...................................................................................... ............ 161 19.2.7 mess age signal interrupt regis t ers ...................................................................................... ........... 163 19.2.8 doorbell and mis c ellan eous interrupt regis t ers .......................................................................... .... 164 19.2.9 extended registers ...................................................................................................... .................... 168 19.2.9 . 1 address translation contro l reg i sters ............................................................................................................. 169 19.2.10 general c ont rol regis t ers .............................................................................................. .............. 174 19.2.11 power mana gement regis t ers ............................................................................................. ........ 175 19.2.12 hot sw ap regis t ers ..................................................................................................... ................. 178 19.2.13 vpd regis t ers .......................................................................................................... .................... 179 19.3 n on -t ransparent m ode o peratio n ...................................................................................................... 180 19.4 i nter rupts ............................................................................................................................... ............... 181 19.4.1 direc t mes s age interrupts ............................................................................................... ................. 181 19.4.1 . 1 direct message interrupt operations ................................................................................................................ 181 19.4.2 doorbell interrupts ..................................................................................................... ....................... 181 19.4.2 . 1 doorbell in terru pt operations ......................................................................................................................... 181 19.4.3 mess age signaled interrupts (msi) ....................................................................................... ........... 181 19.4.3 . 1 m s i operation ............................................................................................................................... ................ 182 19.5 n on -t ransparent m ode b oo t u p s equence ........................................................................................ 183 19.5.1 usi ng xb_m e m input to avoid initial retry lat ency ....................................................................... . 183 19.6 n on -t ransparent a pplicatio n s ys t e m c onfi gura ti on o verview ...................................................... 185 19.6.1 memory allocation re gis t ers initialization .............................................................................. .......... 185 19.6.2 bas i c initialization sequenc e ........................................................................................... ................. 186 19.6.3 exam ple of addr ess setup and mappi ng .................................................................................... ..... 187 20 ieee 1149.1 comp atibl e jtag cont rol l er .................................................................................. 189 21 eeprom ...................................................................................................................... ............................... 190 21.1 a ut o m ode e eprom a ccess ................................................................................................................ 190 21.2 eeprom m o d e at r eset ....................................................................................................................... 190 21.3 pci 6254 r ev aa only : e eprom a utol oa d in n on -t ransparent m ode ............................................ 190 21.4 eeprom d ata s tr uct ur e ..................................................................................................................... 191 21.4.1 eeprom address and co rrespondi ng pci 6254 register ............................................................. 192 22 vital pr oduct data .......................................................................................................... .................. 194 23 pci power manage me nt ........................................................................................................ ............ 195 23.1 p_pme# and s_pme# signals . .............................................................................................................. 195 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 12 24 hot swap .................................................................................................................... ............................. 196 24.1 e arl y p ow e r s uppo rt ........................................................................................................................... 196 24.2 a s s i gnme n t of h ot s wap p or t .............................................................................................................. 196 24.3 h ot s wap s ig n a l s ............................................................................................................................... .... 197 24.4 h ot s wap r egister contr o l and s t atu s .............................................................................................. 197 24.5 a voidin g i niti all y r etry or i nitia l l y n ot r espo nding r equireme nt .................................................. 197 24.6 d evice h iding ............................................................................................................................... ........... 198 24.7 i mplementin g h ot s wap c ontr olle r us ing pci 62 54 gpio pins ......................................................... 198 25 package spec ificat i o ns ...................................................................................................... ............. 199 26 electri c al specifications ................................................................................................... ........... 201 26.1 m aximum r ating s ............................................................................................................................... ..... 201 26.2 f uncti o nal o perating r ang e ................................................................................................................ 201 26.3 dc e lectric a l c haracte r istics ............................................................................................................ 201 26.4 pci s ignal t im i n g s peci f icatio n ............................................................................................................ 202 26.4.1 pci si gnal ti m i ng ....................................................................................................... ...................... 202 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 13 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 14 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 15 1 register index when looking up registers, please also check registers below preceded with ?primary? or ?secondary?. arbiter control register .............................................................. 49 non-transparent, primary ..................................................... 175 bridge control register....................................................... 46, 141 cache line size register ........................................................... 43 non-transparent, primary ..................................................... 138 capability identifier ................................................................... 163 non-transparent, primary ..... 69, 70, 71, 72, 176, 177, 178, 179 chip control register non-transparent, primary ............................... 48, 153, 154, 174 class code register ................................................................... 43 non-transparent, primary ..................................................... 138 clkrun register ........................................................................... 64 device id register ...................................................................... 42 non-transparent, primary ..................................................... 136 diagnostic control register ........................................................ 49 non-transparent, primary ..................................................... 175 downstream bar 0 translation address non-transparent, primary ..................................................... 171 downstream bar 0 translation mask non-transparent, primary ..................................................... 172 downstream bar 1 translation address non-transparent, primary ..................................................... 171 downstream bar 2 translation address non-transparent, primary ..................................................... 171 downstream i/o or memory bar 0 non-transparent, primary ..................................................... 139 downstream memory bar 1 non-transparent, primary ..................................................... 139 downstream memory bar 2 non-transparent, primary ..................................................... 139 ecp pointer ................................................................................ 46 non-transparent, primary ..................................................... 140 eeprom address .............................................................. 59, 152 eeprom control.................................................. 58, 59, 151, 152 gpio input data register ........................................................... 61 non-transparent, primary ....................................... 66, 158, 160 non-transparent, primary ............................................... 67, 160 gpio output data register ........................................................ 61 non-transparent, primary ....................................... 66, 158, 159 non-transparent, primary ............................................... 67, 160 gpio output enable register..................................................... 61 non-transparent, primary ....................................... 66, 158, 159 non-transparent, primary ............................................... 67, 160 header type register................................................................. 44 non-transparent, primary ..................................................... 139 hot swap register non-transparent, primary ............................................... 71, 178 hot swap switch non-transparent, primary ............................................... 65, 159 i/o base address upper 16 bits register................................... 46 i/o base register........................................................................ 44 i/o limit address upper 16 bits register ................................... 46 i/o limit register ........................................................................ 44 internal arbiter control register ......................................... 57, 150 interrupt pin register .................................................................. 46 non-transparent, primary ..................................................... 140 memory base register ......................................................... 45, 65 memory limit register .......................................................... 45, 65 message address non-transparent, msi ........................................................... 163 message data non-transparent, msi ........................................................... 163 message interrupt status non-transparent, primary ............... 68, 164, 165, 166, 167, 168 message upper address non-transparent, msi............................................................163 miscellaneous options ........................................................52, 145 next item pointer.......................................................................163 non-transparent, primary....................69, 71, 72, 176, 178, 179 p_serr_l event disable register ............................................60 non-transparent, primary......................................................156 p_serr_l status register ........................................................63 non-transparent, primary......................................................157 pmcsr bridge support non-transparent, primary................................................70, 177 power management capabilities non-transparent, primary................................................69, 176 power management control/ status non-transparent, primary................................................70, 176 power up status register ...................................................66, 160 prefetchable memory base register...........................................45 prefetchable memory base register upper 32 bits..............45, 65 prefetchable memory limit register ...........................................45 prefetchable memory limit register upper 32 bits ..............46, 65 primary bus number register.....................................................44 primary command register ........................................................42 non-transparent, primary......................................................136 primary flow through control register ..............................50, 143 primary latency timer register..................................................43 non-transparent, primary......................................................139 primary side incremental prefetch count ...........................54, 147 primary side maximum prefetch count ..............................55, 148 primary side prefetch line count .......................................54, 147 primary status register ..............................................................43 non-transparent, primary......................................................138 revision id register....................................................................43 non-transparent, primary......................................................138 secondary bus number register................................................44 secondary clock control register ..............................................62 non-transparent, primary......................................................154 secondary flow through control register .........................56, 149 secondary latency timer ...........................................................44 secondary message register non-transparent, primary..............................................161, 162 secondary side incremental prefetch count ......................55, 148 secondary side maximum prefetch count .........................55, 148 secondary side prefetch line count ..................................54, 147 secondary status register..........................................................45 software register non-transparent, primary......................................................153 subordinate bus number register..............................................44 subsystem vendor id non-transparent, primary......................................................140 timeout control register ...................................................51, 144 upstream bar 0 translation address non-transparent, primary......................................................169 upstream bar 0 translation mask non-transparent, primary......................................................170 upstream bar 1 translation address non-transparent, primary......................................................169 upstream bar 2 translation address non-transparent, primary......................................................169 vendor id register......................................................................42 non-transparent, primary......................................................136 vpd data register non-transparent, primary................................................72, 179 vpd register non-transparent, primary................................................72, 179 2 ordering information part number rev. descripti o n pc i 62 5 4 aa dual m o de un i v ersal pc i-t o- pc i bri dge pc i 62 5 4 ab dual m o de un i v ersal pc i-t o- pc i bri dge pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 16 3 using the pci 6254 3.1 transparent m o de application since the pci 6254 prima r y and secon d a ry port s are asyn chrono u s to each oth e r, the two in depe ndent system s can run at different fre que n c ie s. it is possible to ru n the secon d a r y bus fa ster tha n the primary bus. pci 6254 ha s powe r ful pro g ramm able b u ffer co ntrol, whi c h can be use d to regul ate data thro ughp ut for multiple pci maste r s on the se co n dary po rt. the data prefet ch size ca n be prog ramm ed up to 256 bytes. in tran spa r e n t mode, the host sy stem pci bus i s co nne cted to the pci 6254 p r imary po rt. the seco nda ry pci port ca n use either a custo m desig ned e x ternal arbiter or the pci 6254 internal a r biter. desi gn ers can eith er use cu stom de sig ned cl ock ge neratio ns, o r the pci 6254 s_clk[9: 0] o u tputs de rive d out of the primary po rt pci clo ck input or an ex ternal o scill ator, to provide clo c ks to se conda ry pci device s and th e pci 6254 s _ clkin in put . primary port and second a r y port have i ndep ende nt pci reset inp u ts. s_rstin# is feed-ba ck from the s_rsto ut# . in tran spa r e n t application , xb_mem must be set to ?0 ?. only software can p r og ram spe c ial m e mory ra nge regi sters to re serve a p r ivat e memory re gion for se co ndary po rt de vices u s e o n l y . pci 6254 will not re spo nd to any acce ss to this private memory regio n by any seconda ry pci ma sters o r pri m ary pci ma sters. the ba sic d e s ign id ea is o p timized fo r the followi ng: s-p o rt pc i 62 54 p-p o rt pci device s + priv ate me mor y region t r ans# = 0 u_mod e = x xb_m e m = r e served to 0 s_cfn# = optional 0 or 1 p_boot = x 10 s_cl kn = use optional s_rst out # = used p_rst out # = not used se c o nd ar y bu s host system back-p la ne pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 17 3.2 standard non?transparent application the pci 625 4 non - tran sp arent mo de a c ts a s a mem o ry mapp ed pci device o n a pci back-plane. the p c i 6254 primary si de i s used to co n nect to the pci back-plan e, like that of the tran sp arent mode ap p lication s . the intelligent sub s ystem i s co n necte d to t he secon d a r y port the sub s ystem c an u s e eithe r an e x ternal arbiter or the pci 6254 internal a r bite r. subsyste m clo ck g ene rat i on is ge neral ly achieved u s ing a clo ck synthesi z er to provide cpu clo c ks, su bsy s tem pci clo c ks to su bsy s tem pci device s and the p c i 6254 s_ clkin input. howeve r it can also the pci 6254 s _ clk[9:0] out puts de rived out of the primary port pci clock input o r an extern al oscillator the p_boot pin sho u ld b e prog ram m a b le to ?0? su ch that the subsyste m at seco nda ry port has hig her b oot prio rity. the subsy s tem mu st either setu p the bar re gi sters first or the xb_mem option mu st be active for the primary po rt host to be abl e to complete its system ini t ialization seq uen ce. the u s e of xb_mem option forces pci 6254 to de cla r e a fixed 16 m memory wi ndo w for cro s s-b r id ge com m unication at powe r up. if necessa ry, this window s i ze c an be c h anged by eepr om or software after power up. primary port and second a r y port have i ndep ende nt pci rese t inp u ts. de sign ers ca n either u s e custo m de sign ed re set or the pci 6254 s_ rsto ut# for the second a r y port and su bsyste m re se t. the ba sic d e s ign id ea is o p timized fo r the followi ng: s-p o rt pc i 62 54 p-p o rt cpci back -plane sub-syst em p_req# & s_gn t# t r ans# = 1 u_ mod e = 0 xb_m e m = optional 0 or 1 s_cfn# = optional 0 or 1 p_boot = 0 s_re q0# & s_gnt 0# = used 8 s_re qn# & s_ gnt n# = use optional 10 s_cl kn = use optional s_rst out # = use optional p_rst out # = not used p_clkin p_rstin# p_inta# pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 18 3.3 universal bridging application pci 6254 is d e sig ned su ch that it allows the desi gn of an intelligent sub s ystem to act as a ho st or as a me m o ry mappe d devi c e by setting the u_m o de (unive rsal mode) pi n to ?1 ?. whe n actin g as a ho st, the sub s ystem u s e s the pci 6 254 universal tran spa r ent mode. the su bsyste m pci bus is co nne cted to the pci 6254 prima r y port. the su bsystem uses ei ther an external arbite r or an arbite r tha t is built-in to the north b r idge for sub s y s te m pci bus su pport. as for t he ba ck-pla n e pci arbiter, either a cu st om desi gne d arbi ter or the pci 6254 internal arbiter can b e use d . subsystem clo c k g eneration is g enerally achi eved usin g a clo c k synthe sizer to provide cp u clo c ks, sub s ystem pci cl ocks to sub s ys tem pci dev ice s and the pci 6254 p_ clki n input. de si gners can eit her u s e custo m desig ned clock output s, or the pci 62 54 s_clk[9: 0] outputs deriv ed out of the primary port pci clock input or an external osc illator, to drive the pci back-plane. whe n actin g as an intelli ge nt sub s ystem behaving a s a memory ma pped pci dev ice on the b a c k-pla ne pci bus, the sub s yste m use s the pci 6254 univ ersal no n-t r a n sp are n t mod e . the pci 6254 external arbiter mo de is sele cted so that the s_re q0# an d s_g n t0# a c t a s the pci_re q # and pci_g n t# respe c tively for direct con n e c tion to back-pl ane o r cu stome r arbiter interfa c e . t he p_boo t pin sho u ld be co nne cted to 1 indicatin g that the primary p o rt has boot p r iority. the su bsyste m at the pr imary po rt must either setup the ba r regi ste r s first or the xb_mem option must be active for t he ho st from t he seco nda ry port to be able to compl e te its system initialization seque nce. the use of xb_m e m option force s pci 6254 to declare a fixed 16 m me mory win d o w for cross-bridge comm uni cati on at power up . if necessary, this window si ze c an be changed by eeprom or software after power u p . the ba sic d e s ign id ea is o p timized fo r the followi ng a s suming the same cpu b oard b ehavin g differently: p-p o rt pc i 62 54 s-p o rt t r ans# = 0 u_ mod e = 1 xb_m e m = 0 s_cfn# = optional 0 or 1 p_boot = x s_clkin = f eed f r o m s_cl k9 or custo m clock gener a tions s_rst out # = used to dr ive slots and inter n al feedback to secondar y interface s_rst i n# = not used, pull high p-p o rt pc i 62 54 s-p o rt t r ans# = pull- high u_ mod e = 1 xb_m e m = optional 0 or 1 s_cfn# = x p_boot = 1 p_rst out # = use optional s_cl k[9:1] = not used s_cl ki n = not used s_rst i n# = not used, pull high cpci back -plane sa m e cpu board acting as subsyst e m for use in peri pheral slot sa m e cpu board acting a s ho st fo r use in syste m slot sub-system built-in arbiter built-in clock 9 s_re qn# and s_gnt n# or custom ar biter s_cl k[9:0] or custo m clock gener a tions s_re q0# & s_gnt 0# s_cl k0 acts as clock input sub-system built-in arbiter built-in clock s_rst out # acts as r e set input s_inta# s_rst out # or custo m r e set generation pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 19 3.3.1 uni versal mode clk, rst#, req# , gnt# and sysen# si gnal connections the pci 625 4 allows a ju mper le ss aut omatic switch betwe e n cp ci system slot or periph eral slot applications. in universal mode, the pci 6254 switch es bet wee n syst em and pe riphe ral mo de using the t r ans# input pi n. the tra n s# pin is designed for direct connection to the cpci sysen# pin. whe n tra n s# is ?0 ?, the pci 6254 swi t che s to the univ ersal t r a n sp are n t mod e in whi c h the pci 6254 dri v es out s_rsto ut# to the back-p l ane a s well a s ena ble s the use of the s_rsto ut # internal fee d b a ck for secon dary reset. s_rst i n# input is in ternally ?and? with the s_ rsto ut# fe edba ck and should b e tied to ?1? o r ca n be fed with c u s t om res e t input. sec o ndary port logic u s e s the s_clkin. desig ner sho u l d use, for exa m ple, s_clk 9 to feed the s_clkin with a cl ock tra c e len g th that matches the b a ck-plane clo ck trace s len g th. if custom a r bit e r is not use d , s_req0# a nd s_gnt 0# ca n be di re ctly con n e c ted to the back-plan e. whe n tra n s# is ?1 ?, the pci 6254 swi t che s to the universal no n-t r an spa r e n t mode in whi c h the pci 62 54 three - state s the s_rst o ut# to allow b a ck-pl ane rs t# to drive the s_rsto ut# pin whi c h acts a s se co ndary re set input. s_rstin# in put is intern al ly ?and? with the s_rsto ut# feed ba ck and sho u ld be tied to ?1? or ca n be fed with custom reset input. the s_ clkin pin in put is igno red inside the p c i 6254 a nd the seco nda ry port logic u s e s the s_clk0 inte rnal feed ba ck as seconda ry clock input. s_cfn# is ?don?t care ? and if cu stom arbite r is not use d , s_req 0# and s_g n t0# ca n be di rectly conne cted to the back-pl ane. hot s w a p pi n enum # mu st be han dled with cu stom l ogic for u n ive r sal a ppli c atio ns. the followi ng is an exampl e of universal mode co nne ction s (u_mo d e is set to ?1?): pi n name d e sc r i pt ion t rans # connect to cpc i sy sen # pin u_mode s _ cf n# s_c l k 0 s_c l k in s_c l k 9 s_r s t in# s_r s t out# s_req0# s_g n t0# syst em slot applic at ion using p c i 6254 arb i ter 0 use us_c l k i n as secondar y port input clock 1 0 outp ut inp u t e.g. f r om s_c l k 9 outp ut not u s ed outp ut req0# inp u t g n t0# outp ut syst em slot applic at ion u s i n g extern al arb i ter 0 use us_c l k i n as secondar y port input clock 1 1 outp ut inp u t e.g. f r om s_c l k 9 outp ut not u s ed outp ut custom arb i ter gnt # inp u t custom arb i ter re q# outp ut p e ri p h eral s l ot applic at ion using p c i 6254 un i v ersal mod e 1 use s _ c l k i n as secondar y port input clock 1 x used as s econ d a ry clock inp u t i gno red in pci 6254 not us ed outp u t not us ed not u s ed used as se c o ndar y reset inp u t re q# outp ut gn t # inp u t pc i 62 54 s- por t ( u _m od e = 1 , use pc i 6 254 a r biter a s exa m ple) s_clk0 s_rst o ut # s_req0# s_gnt0 # t rans# clk0 rst# req0 # gnt0 # s y sen# back-pl ane connector pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 20 3.4 symmetrical non?transparent application pci 6254 is d e sig ned su ch that it allows the bridgi ng o f two totally in depe ndent system s. the o n ly nece s sary option is to d e cid e whi c h h o st ha s high e r boot pri o rity. the pci 625 4 external arbiter mod e is sele cted so that the s_re q0# an d s_g n t0# a c t a s the pci gnt # and pci req# re spe c tively for hand sh akin g with one of th e host. all pci signal s sh ou ld be co nne ct ed to their respe c tive ho st pci sign als. the boot pri o rity is pro g ra mmable. the highe r pri o rity boot system must eithe r setup the bar regi sters first o r the xb_mem option mu st be acti ve for th e lowe r boot prio rity syste m to be able to compl e te its system initialization se que n c e. the u s e o f xb_mem option forces p c i 6254 to de clare a fixed 16m memory wi nd ow for cro s s-bridg e co mm unication at p o we r up. if nece s sary, this wind ow size can b e ch ang ed by eeprom or s o ftware after power up. the inde pen d ent system should u s e eit her an exte rn al arbite r or a n arbite r that is built-in to th e north b r idg e for its pci bus u s e. system cl ock gen eratio n is gen erally ac hieve d usi ng a clo c k sy nthesi z e r to provide cp u cl ocks, pci clo c ks to system pci d e vice s and th e pci 6254 p c i input. since the pci 6254 prima r y and secon d a ry port s are asyn chrono u s to each oth e r, the two in depe ndent system s can run at different fre que n c ie s. the ba sic d e s ign id ea is o p timized fo r the followi ng: p-p o rt s-p rt pci 6254 o t r ans# = 1 u_ mod e = 0 xb_m e m = optional 0 or 1 s_cfn# = 1 p_boot = pr ogr am m a ble p_rst out # = not used s_rst out # = not used s_re q & sgnt [ 8 :1] = not used s_cl k[9:0] = not used p_i n t a # & s_int a # = used independe nt system built-in arbite built-in clo c ration s independe nt system built-in arbite r built-in clo c k gene ration s r k gene pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 21 4 pin diagram thi s di ag ram depi ct s m a i n l y no n- tra n s p are n t m ode si g n al nam e s. pl ease refe r t o pi n des c ri pt i o n f o r t r ans p are n t m ode sig n a ls t h at are m u lt ip lex e d with no n-tran sparen t si g n a ls. pci 6254 top view s _ rs t o ut # vss pc l k in vss pad 1 6 sad 1 7 pc be4 # sad 5 1 vd d sad 3 9 vss pad 6 2 pad 1 3 vss sad 3 2 ppar 6 4 pad 2 7 vd d 21 t sad 6 2 18 p_ in t a # sg n t 7 # sc l k o 5 sr eq 4 # vss vd d vss pad 1 1 pad 3 4 p i rdy # sad 5 8 sad 4 3 pc be7 # pad 7 sad 4 9 pw r g d sad 4 7 vss sr eq 1 # sg n t 4 # c u sad 3 8 sad 4 4 19 vss sad 3 0 sg n t 6 # sc l k o 2 vd d vss sad 2 4 vss sad 0 vss p t rdy # sad 5 4 sad 3 3 pad 1 0 sad 6 3 pad 3 5 sad 3 4 vss pad 5 8 vd d d v p m 66e n pad 4 2 pad 5 7 20 64e n # gp i o 1 5 pad 2 6 vss sg n t 1 # gp i o 1 vss vd d sad 1 9 vss pst o p # pad 5 5 pad 9 vd d sad 4 2 tc k sad 5 7 pr eq 6 4 # sg n t 2 # vss e w pad 4 0 vd d sad 5 2 pc be6 # gp i o 0 9 u_ m o de vss pad 2 8 pr eq # sr eq 0 # vss sc be3 # vss pl o c k# pad 0 vd d vss vd d sc be4 # pad 2 sc fn # f y sad 6 pvio vss pad 6 1 pad 6 0 sper r # pad 2 1 8 sc l k o f f sg n t 0 # sc l k o 0 sc l k o 1 vd d pad 2 2 sad 2 3 vss vd d pd vsel # pad 5 pad 4 4 vss sad 4 sac k6 # vss g s m 66e n pad 5 2 vss pad 3 vss pac k6 4 # sad 4 8 sg n t 8 # 7 vss vss vd d sr eq 2 # pr st in # sad 2 6 vss aa vss vss vss pc be1 # pad 1 2 sfr a m e # vd d sad 1 5 h sad 1 0 sad 1 sad 5 sad 2 sc be5 # vd d pc be0 # vd d 10 6 vss sc l kst b spm e# vss sr eq 7 # vss vss vss ab vd d pper r # vss sad 5 9 sst o p # j s t rdy # vd d sser r # sad 9 sad 3 sc be7 # sad 1 3 pad 4 7 pad 4 5 11 5 sr eq 5 # vss vss pad 3 1 pad 2 3 sg n t 3 # sad 2 7 pad 1 8 ppar vss pad 4 1 vss k pad 3 6 sad 7 sc be2 # sad 1 4 sad 8 vd d pad 4 6 pad 1 pad 5 6 12 4 pad 8 vss vss n c sc l k o 4 pad 1 9 vss sc l k o 7 sg n t 5 # pad 2 0 pad 1 4 pc be5 # vss l ac vss sc be0 # pad 3 9 spar vd d vss vd d sc be1 # pad 4 13 vss pad 5 0 pid sel vss vd d vss vd d gp i o 3 vd d pg n t # gp i o 2 b p cce a vd d vss m pser r # pad 3 7 sl o c k# sr eq 6 4 # svio vss sad 3 7 vd d 14 sad 5 5 sad 6 1 vss pad 2 9 3 vss gp i o 4 vss sr eq 6 # pc be3 # sr eq 3 # vd d pad 1 7 vss sad 2 0 vss vd d sad 1 2 td o sad 6 0 vss 15 vd d sad 5 0 sad 5 6 sad 5 3 pad 6 sr eq 8 # 2 gp i o 5 gp i o 8 vd d vd d sad 2 8 pc be2 # vss sad 2 2 pad 1 5 sad 1 1 pad 4 9 s i rdy # vss spar 6 4 sad 4 6 sad 4 1 16 vd d m skin vss tr s t # pad 3 2 vd d sc l k o 6 1 n gp i o 9 vd d sc l k o 8 sad 3 1 pad 3 0 pad 2 5 vss vss vss sad 2 1 pad 4 3 pad 3 3 sad 1 6 pad 5 1 sad 4 0 tm s sd vsel # vss pad 5 3 sc be6 # vd d sad 4 5 sc l k o 3 pad 2 4 22 p gp i o 1 0 gp i o 1 1 vss sad 2 9 sc l k vd d pfr a m e # sad 2 5 sad 1 8 td i pad 4 8 vd d sad 3 5 b pad 3 8 pad 5 4 pad 6 3 pad 5 9 cf g6 6 sad 3 6 sc l k o 9 23 r 17 gp i o 1 4 gp i o 1 2 sr st in # ee_ en # ppm e # vd d gp i o 6 pr s t o u t # eep c l k gp i o 1 3 e num # sid sel eep d a t a l_ st a t t r ans # p _ boot vd d t est # ej ec t _ en # ej ec t s_ in t a # gp i o 7 xb _ m em o s c sel# os c i n vd d pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 22 5 signal definition signal t y p es pi pci input (5v signal in put tolera nt, i/o vdd=3.3v ) pts pci thre e-state bi-di r e c tio nal (5v si gnal input tolerant , i/o vdd=3. 3v) po pci output psts pci sustaine d thre e-state output. (5v sign al input tolera nt, i/o vdd=3.3v ) i cmos input o cmos outp u t io cmos bi-direc t pu signal is pull ed-u p internal ly pd signal is pull ed-d o wn internally 5.1 primary bus interface signals n a m e t y p e des c r i p t i o n p _ a d [ 3 1 : 0 ] p t s primar y address/da ta : m u ltiplexed ad dre ss a nd dat a bus. add r e ss i s indicated by p_frame# a s sertion. writ e data is sta b l e and valid when p_irdy# i s a s serted a nd read data i s st able an d valid whe n p_trdy# is asserte d . dat a is tran sferre d on ri si ng cl ock edg es wh en both p_irdy# and p_trdy# are asserte d . during b u s idl e , pci 6254 dri v es p_ad to a valid logic level wh en p_gnt# i s asse rted. p _ c b e [ 3 : 0 ] p t s primar y command/b y te enables : multi p lexed comm and field an d byte enabl e field. duri ng ad dre ss p h a s e, the initiator drive s the tran sa ct ion type on these pin s . after that th e initiator driv es the byte e nable s du ring data pha se s. duri ng bu s idle, pci 6254 d r ive s p_cbe[3:0] to a valid logic level whe n p_gnt # is asse rted. p _ p a r p t s primar y pari t y : parity is even across p _ ad [31:0], p_cbe[3:0], and p_par (i.e. an even numbe r of ?1?s). p_par is an input an d is valid and stable on e cycle afte r the address ph ase (i ndi cate d by assertio n of p_fram e#) for address pa rit y . for write d a ta pha se s, p_par is an in put and is vali d one clo ck afte r p_irdy# is a sserted. fo r rea d data pha se, p_par is an output and is valid o ne clo c k after p_trdy# i s asserte d . signal p_par is three- stated on e cy cle after the pad lines a r e three-stated. durin g bu s idle, pci 6254 d r ives p par to a valid logic level whe n p_gnt # is asse rted. p _ f r a m e # p s t s primar y frame : driven b y the initiator of a transacti on to indicate the begin n ing an d duratio n of an acce ss. the dea ssertio n of p_fram e# indicates the final data pha se re que sted by the initiator. before bein g three - stated, it is driven to a dea sserted state for one cycle. p _ i r d y # p s t s primar y irdy : driven by the initiator of a transaction to indicate its ability to compl e te the curre n t data pha se on the prima r y side. once asse rte d in a data pha se, it is not dea sserted until en d of the data pha se. before being three-s t ated, it is driven to a dea sserted state for on e cycle. p _ t r d y # p s t s primar y trdy : driven by the target of a trans action t o indicate its ability to compl e te the curre n t data pha se on the prima r y side. once asse rte d in a data pha se, it is not dea sserted until en d of the data pha se. before being three-s t ated, it is driven to a dea sserted state for on e cycle. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 23 p _ d e v s e l # p s t s primar y dev i ce select : asserte d by the target indi cati ng that the de vice is acceptin g the transa c tion. as a maste r , pci 6254 wai t s for the assertion of this sig nal wit h in 5 cycl es o f p_frame# assertio n; otherwi se, termi nate with maste r abo rt. before bein g three-stated, it is driven to a deasse rted state for one cy cle. p _ s t o p # p s t s primar y sto p : as s e rted by the target indic a ti n g that the target is re que sting the initiator to stop the cu rrent tran sact io n. before bei ng three - stated, it is driven to a de asserte d stat e for one cycl e. p_lock # p i primar y lock : as serted by mas t er for multiple transac t ions to c o mplete. if lock fun c tio n is not nee d ed, as in the ca se that no se con dary p c i device s sup port lo ck, this input should b e pull ed ?hi g h? an d sho u ld not be con n e c ted to the pci bus. this fun c tion can al so b e d i sabl ed by set t ing regi ster 4 6h b i t 13 to 0. p _ i d s e l p i primar y id select . used a s chi p sel e ct l i ne for type-0 config uratio n acce ss to pci 6254 configuration space. p _ p e r r # p s t s primar y pari t y error : asserted when a data parity error i s dete c te d for data received on t he prim ary interface. before being three - stated, it is d r iven to a dea sserted state for one cycle. p _ s e r r # p s t s primar y s y stem error : ca n be driven l o w by any d e vice to indi cate a system e r ror con d ition. pci 6254 drive s this pin du rin g tran sp are n t mode and when p_ boot = 0 du ring non - tra n sp are n t mod e . x addre s s parit y error x posted write data parity error o n target bus x secon d a r y bus s_serr# asserted x maste r abo rt durin g po sted write tran sa ction x targ et abort durin g po sted write tran sa ction x posted write tran sa ction di scard ed x delaye d write reque st discarde d x delaye d rea d reque st discarde d x delaye d tran sa ction ma ster timeout this signal sh ould be p u lle d up throu gh an external re sisto r . p _ r e q # p t s primar y request : thi s is asserte d by pci 6254 to in dicate that it want s to start a tran sa ction on the p r imary bu s. pci 6254 d e a s sert s this pin for at least 2 pci cl ock cycl es b e f ore asse rting it again. p _ g n t # p i primar y grant : whe n asserted, pci 62 54 ca n acce ss the prim ary bus. duri ng idle a nd p_gnt# a s serted, pci 6254 will driv e p_ad, p_cbe and p_par to valid logic level. p _ m 6 6 e n p i primar y 66 mhz en able: set high for 66mhz p r ima r y bus. thi s signal, along with the s_m 66en si gnal, controls the freque ncy outp u t to the sclkout pins. see ch apter 15 fo r more d e tails pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 24 5.2 primary bus interface 64-bit extension signals n a m e t y p e des c r i p t i o n p_ad[63:32] p t s primar y address/data up per 32-bits : multiplexed a ddre s s and d a ta bus provide 32 extra pins . during addre s s phase (when us ing the dac c o mmand and when p_ req64 # is a s serted ), the uppe r 32 -bits of a 64-bit ad dre ss a r e transfe rred; o t herwi se, the s e bits a r e un defined. duri ng a data ph a s e, an addition al 32-bit data is tra n sferre d if a 64-bit tran sa cti on is ne gotiat ed by the assertio n of p_req6 4# an d p_ack64#. p _ c b e [ 7 : 4 ] p t s primar y command/b y te enables up per 4-bi ts : co mmand a nd b y te enable fields (m ultipl exed). du rin g addre s s pha se (whe n usi ng the dac comman d and when p_ req64 # is a s serted ), the actual b u s co mmand i s tra n sferre d on these pin s ; otherwi se, these bits are undefin ed. during a d a ta p hase, they indicate whi c h byte la nes carry me aningful d a ta if a 64-bit tran sa ction is negotiate d by the assertion of p_req64 # and p_ack 64#. p _ r e q 6 4 # p s t s primar y request 6 4 -bi t transfer : wh e n asserte d by the current b u s maste r , indicates it desi r e to transfe r da ta using 6 4 -bi t s. pci 6254 i gnores this input du ri ng re set and assert s p_re q64# whe n e v er the se con dary pci maste r tran sf ers in 6 4 bit or the force 64 option i s e nable d . p _ a c k 6 4 # p s t s primar y ackno w l e dge 6 4 - bit tran sfer : when a s sert ed by the targ et device, indi cates it is willing to trans fer data using 64-bits. it has the same timing as p_devsel#. when deasserting, it is dr iven high for one cycl e before th ree - stated. p _ p a r 6 4 p t s primar y interfac e upp e r 32-bi t parit y : this provide s the even pa rity bit that prote c ts p_a d [63:32] an d p_cbe[7:4]. it must be valid one cl ock a fter each address ph ase on any tran sa ction in whi c h p_re q64 # is asse rted. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 25 5.3 secondary bus interface signals n a m e t y p e des c r i p t i o n s_ad[31:0] pts seconda r y a ddress/ da ta : multiplexed address an d data bu s. addre ss i s indicated by s_frame# a s sertion. writ e data is sta b l e and valid when s_irdy# i s a s serted a nd read data i s st able an d valid whe n s_trdy# is asserte d . dat a is tran sferre d on ri si ng cl ock edg es wh en both s_irdy# and s_trdy# are asserte d . during b u s idl e , pci 6254 dri v es s_ad to a valid logic level wh en the s_gnt# is a s serte d . s_cbe[3:0] pts seconda r y c o mmand/b y te enables : multiplexed co mmand field and byte enabl e field. duri ng the ad dre ss p h a s e, the initiator drives the tran saction type on these pins. after that the initia tor drives the by te enable s du ring data pha se s. duri ng bu s idle, pci 6254 d r ive s s_cbe[3:0] to a valid logic level whe n the inte rnal g r ant is a s serted. s_par pts seconda r y parit y : parity is even a c ro ss s_ad[31:0] , s_cbe[3:0], and s_par (i.e. an even numb e r of ?1?s). s _ par is an in put and is vali d and stable o ne cy cle after the a ddre s s pha se (indicated by assertion of s_frame# ) for add re ss p a rity. for writ e data pha se s, s_par is an input and is valid o ne clo c k after s_irdy# is asserte d . for read data p h a se, s_par is an output and i s valid one cl ock after s_t r dy# is a s sert ed. signal s_par is three-stated on e cycle afte r th e s_ad line s are three-stat ed. duri ng bu s idl e , pci 6254 d r ives s_par to a valid logic level wh en the internal g r a n t is asse rted. s_frame# psts seconda r y f rame : drive n by the initiator of a transaction to indi cate the begin n ing an d duratio n of an acce ss. the dea ssertio n of s_fram e# indicates the final data pha se re que sted by the initiator. before bein g three - stated, it is driven to a dea sserted state for one cycle s_irdy# psts seconda r y irdy : driven by the initiator of a transact i on to indicate its ability to complete t he cu rrent da ta phase on the prim ary si de. once asserted in a data pha se, it is not dea sserted until en d of the data pha se. before being three-s t ated, it is driven to a dea sserted state for on e cycle. s_trdy# psts seconda r y t rdy : driven by the target of a tr ansacti on to indicate its ability to complete t he cu rrent da ta phase on the prim ary si de. once asserted in a data pha se, it is not dea sserted until en d of the data pha se. before being three-s t ated, it is driven to a dea sserted state for on e cycle. s _ d e v s e l # p s t s seconda r y d e v i ce select : asse rted by the target indi cating that th e device is acce pting the tran sa ctio n. as a ma ste r , pci 6254 waits for the a s sertio n of this sig nal wit h in 5 cycl es o f s_frame# assertio n; otherwi se, termi nate with maste r abo rt. before bein g three-stated, it is driven to a deasse rted state for one cy cle. s _ s t o p # p s t s seconda r y stop : asse rte d by the targe t indicating th at the target is requ estin g the initiator to stop the cu rre nt transaction . before bein g three - stated, it is driven to a dea sserted state for one cycle. s_lock # psts sec o ndary lock: as serted by mas t er t o c o mplete mult iple transactions. s_perr# psts seconda r y parit y error : asserted whe n a data parity error is d e tect ed for data re ceived on the prima r y interface. before bei ng three - state d , it is driven to a deasse rted state for o ne cycl e. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 26 s _ s e r r # p s t s seconda r y sy stem error : can be d r ive n low by an y device to indicate a system e r ror con d ition. pci 6254 drive s this pin only d u ring non - t r ansparent mode with p_ boot = 1 an d if the following: x addre s s parit y error x posted write data parity error o n target bus x primary p_s e rr# a s se rted x maste r abo rt durin g po sted write tran sa ction x targ et abort durin g po sted write tran sa ction x posted write tran sa ction di scard ed x delaye d write reque st discarde d x delaye d rea d reque st discarde d x delaye d tran sa ction ma ster timeout this signal sh ould be p u lle d up throu gh an external re sisto r . s_req#[0] pts seconda r y r e ques t 0 : wh en external a r bitratio n is not ac tivated, this is asserte d by external device to indicate t hat it wants to start a tran saction o n the secon d a r y bus. it must be externally pulled up through resi sto r s to vdd. whe n extern al arbitration i s active, th is become s the external gra n t input to pci 6254. whe n unive r sal mod e is a c tive and whe n operated in internal arbit r ation mode, this is the pci 6254 secon d a r y port req u e s t output. s_req#[8:1] pi seconda r y r e ques t s : thi s is a s serted by external devic e to indicate that it want s to start a transaction on the seco ndary bu s. th ey must be e x ternally pulled u p thro ugh re si stors to vdd. s_gnt#[0] pts seconda r y gran t 0 : this pin behave s like s_g n t#[ 8 :1] under t r ansparent mode an d external a r bitrati on is not a c tivated. whe n extern al arbitration i s active, this become s the external bus req u e s t output from p c i 6254. whe n unive r sal mod e is a c tive and whe n operated in internal arbit r ation mode, this is the pci 6254 secon d a r y port gra n t inpu t. s_gnt#[8:1] po seconda r y gran ts : pci 6254 a s sert s this pin to access the se co ndary bu s. pci 6254 de a s sert s this pin for at least 2 pci clo ck cycles befo r e a s sertin g it again. durin g idle and s_g n t# a s serte d , pci 6254 wi ll drive s_ad, s_cbe and s_par to valid logic l e vels. s _ m 6 6 e n p t s seconda r y 6 6 mhz en able: drive low if p_m66en is low, otherwi se driven from outsi de to sele ct 66m hz o r 33m hz. this si gnal, along with the p_m66en sig nal, controls t he frequ en cy output to the s_clko utn pins. this pin sho u l d be pulled high or lo w ex ternally. see chapter 15 for more details pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 27 5.4 secondary bus interface 64-bit extension signals n a m e t y p e des c r i p t i o n s_ad[63:32] p t s seconda r y a ddress/ da ta upper 32-bits: multiplexe d address an d data bus p r ovide 3 2 extra pins. duri ng ad dre ss p h a s e (wh en usi ng the dac comm and a n d whe n s_re q64# i s asse rted), the up p e r 32 -bits of a 64-bit address a r e tran sferred; ot herwise, these bits are u n d e fined. du rin g a data pha se, an ad ditional 32 -bit data is tran sf erred when a 64-bit tra n saction has been n egotiat ed by the assertion of s_req64# an d s_ack64 # . s _ c b e [ 7 : 4 ] p t s seconda r y c o mmand/b y te enables upper 4-bits : multiplexed command field and byte enable field. duri ng ad dre ss p h a s e (wh en usi ng the dac comm and a n d whe n s_re q64# i s asse rted), the a c tual bu s com m and is transfe rred o n these pi ns; otherwise, t hese bit s are u ndefine d . during a data pha se, they indicate whi c h byte lanes carry mea n ingf ul data wh en a 64-bit transactio n h a s be en ne go tiated by the assertio n of s_req6 4# an d s_ack64#. s _ r e q 6 4 # p s t s seconda r y r e ques t 64 -bi t trans f er : whe n asse rted by the current bus maste r , indicates it desi r e to transfe r da ta using 6 4 -bi t s. pci 6254 i gnores this input du ri ng re set and assert s s_re q64# whe n e v er the prima r y pci maste r tran sf ers in 6 4 bit or the force 64 option i s e nable d . s _ a c k 6 4 # p s t s seconda r y a ckno w l e dge 64-bi t trans f er: when a sserted by the target device, indi cates it is willing to trans fer data using 64-bits. it has the same timing as s_devsel#. when deasserting, it is dr iven high for one cycl e before th ree - stated. s _ p a r 6 4 p t s seconda r y inter f ac e upp e r 32-bi t parit y : provides even parity bi t that prote c ts s_a d [63:32] an d s_cbe[7:4]. it must be valid one cl ock a fter each address ph ase on any tran sa ction in whi c h s_re q64 # is asse rted. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 28 5.5 clock related signals n a m e t y p e des c r i p t i o n p _ c l k i n i primar y clk input: provi des timing fo r all transa c tio n s on p r ima r y interface. s _ c l k i n i seconda r y c l k input: provides timing for all tran sa ctions on se co ndary interface exc ept du ring un iversal non - t r an spa r e n t mode (u_m ode = 1 and trans# = 1). in universal non - tran spa r ent mod e , this input is ig no red by pci 6254 an d the internal l ogic u s e s the input clo ck from the s_cl k0 pin. s_clk0 i/o seconda r y c l k output: provide s s_cl kin or osci n (if enabl ed ) phase synchro nou s output clo c ks. this cl ock ca n be turne d o ff using the s_clkoff pin. s_cl k0 outp u t is three - sta t ed durin g un iversal non - t r an spa r e n t mode. this allo ws s_clk0 to take the clk sig nal from a cp ci back pla n e for the sec o ndary port logic . when in cpci system s l ot, s_clk0 drives the cpci and when in periphera l slot, back pl ane cl ock driv es s_clk0 pi n. s_clk[9:1] o seconda r y c l k output: provide s s_cl kin or osci n (if enabl ed ) phase synchro nou s output clo c ks. these clo c ks can be tu rne d off using th e s_clkoff pin. s_clko ff i-pd 0 = s_clk[9: 0] output is e nabl e d . this enabl e ca n b e over-ridd e d by mskin input co ntrol s and clo c k ou tput control re gister bit s . 1 = s_clk[9: 0] output are driven lo w. this di sabl e can only be ov er-ridd ed by clock outp u t control regi ster bit s . s_clkin_ stb i-pu 1 = external secon d a r y cl ock pll and s_clkin clo ck a r e stable sign als. 0 = s_rst o ut# will not go inactive unti l s_clkin_s t b is ?1?. if not used, this pin shoul d be co nne cted to 3.3v suppl y. m s k _ i n i seconda r y c l ock disable serial input. this signal i s use d by the hard w a r e mech ani sm to disa ble seconda ry clo ck out puts. th e seri al stream is re ceived by msk_in, starting wh en p_rstin# i s detecte d dea sserted a nd s_rsto ut# is detecte d a s serted. thi s seri al data is use d for sel e ctively disa bling seconda ry clo ck outputs a nd i s shifted into the se con dary clock control co nfig uration regi st er. this inp u t ca n be tied low to enable all se con dary cl ock output s. if tied high, the clo c ks will be active unt il high after re set. after the ?1?s have b e e n shifted in, the clocks will be driven high. o s c s e l # i external oscillator enable. enables co nne ction of e x ternal clo c k for the secondary int e rface. if lo w, secondary bus cl ock out puts will use the clock sign al from o s cin input in stead of p_clkin to gene rate s_clk[9:0]. if high, p_ cl kin is used. this pin m u st not be left unconn ecte d. o s c i n i external oscillator input. external clo c k input u s ed t o gene rate se con dary output clo c ks whe n ena ble d throug h os csel# pin. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 29 5.6 reset signals n a m e t y p e des c r i p t i o n p w r g d i po w e r go od i n p u t : i m p o rtan t: p c i 6 254 re quires a clean lo w to high transi tion p w rgd inpu t. the p w rg d is not internally debounced. i t must b e d e bounce d e x ternally and a hig h inpu t mus t r e fle c t tha t the po w e r is indeed stable. whe n this i nput is l o w, all state m a chine s an d regi sters in pci 625 4 a r e reset and all outputs are t h ree - stated. this hig h input sh ould be 3.3v. importan t: the pwrg d is no t i n tern ally debounce d . it must b e deboun ced exte r nally a nd a hig h input mus t r e flec t tha t the po w e r is indeed s t abl e . its asse rtin g and de asse rting e dge s can be a s ynch rono us to p_clk and s_clk. p_rsto ut# p o prim ary res e t o u tpu t : t h is i s only valid in no n - tra n sp are n t mo de an d it is asserte d wh e n any of the followin g co nd itions is met: 1. signal s _ rstin# is asserte d w hen prim ary port ha s b oot prio rity (pboot =1). 2. the prima r y re set bit in the non - t r ansparent di agno stic cont rol re giste r in config urati on sp ace is set. p _ r s t i n # p i primar y reset: wh en p _ rstin# is active, outpu ts are asyn chron o u s ly three - state d and p_serr# an d p_ gnt # floate d . all primary port pci stand ard conf iguratio n re gisters 0h -3 fh revert to their default state. when a sser ted, all prima r y pci signals are thr ee-s t ated. s _ r s t o u t # p t s seconda r y res e t outpu t : a s serte d when any of th e followi ng condition s i s met: 1. signal p_rstin# is a s serted. 2. the secon dary re set bit in the brid ge c ontrol regi st er (bit 6 regi ster 42h in non - tran spa r ent mo de and regi ste r 3eh in t r an spa r e n t mode ) in config uratio n spa c e i s set. in unive r sal non - tran spa r ent m ode (u_mo d e = 1, tra n s# = 1 ) , thi s output i s di sabled an d s _ rsto ut # pin i s u s e d as the equ ivalent of s_rstin# in put pin. s _ r s t i n # i seconda r y res e t input: in non - tran spa r ent mod e , active lo w input will cau s e all seconda ry po rt control lo gic to re set. prim ary po rt co ntrol logi c i s not affected. in tran spa r e n t or unive r sal mode, this pin is not u s e d and shoul d be pulled high. in universal non - tran spa r ent mod e (u _mode = 1, trans# = 1 ) , this input is igno red a n d s_rsto ut# pin is u s e d as the eq ui valent of s_rstin#. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 30 5.7 hot swap signals n a m e t y p e des c r i p t i o n e n u m # p t s hot s w ap interrupt: an op en drai n bu ssed sig nal to si gnal a chan g e in status fo r the chip. thi s is a n output only sign al. it is asserte d thro ug h the hot swap reg i sters. l _ s t a t i o hot s w a p led: o u tput to indicate the st atus of software conn ectio n p r oc es s . if hot s w ap is not used, l_s t at must be at logic ? 0 ? if eject_e n # is ? 1 ? . ej e c t i hot s w a p eject: pin use d to detect the inse rtion of hot swap devi c e an d is debo un ced in ternally. ho wever so me ex ternal de bou n c e is still recomme nde d. when sign al is asse rted , pci 6254 assert s enum# pin after card initialization is finished . an exte rnal pull low resi st er is recomm ende d. if hot s w a p is not use d , eject must be at logic ? 0 ? if eject_e n # is ? 0 ? . ej e c t _ e n # i ejector pin use ena b le: this pin sho u ld alway s be con n e c ted to logic ?0?. 1 = re se rved and sh ould n o t be use d . 5.8 miscellaneous signals n a m e t y p e des c r i p t i o n s_cf n # i internal a r biter enable : 0 = use internal arbite r. 1 = use external arbite r. if u_mode = 0: s_req0# becom es external arbiter gnt # input a nd s_gnt 0# be come s re q# output to external arbiter. if u_mode = 1: s_req0# becom es re q# output to external arbit e r and s_gnt 0# be come s extern al arbiter g n t# input. cfg 6 6 i primar y config 66mhz : t he state of th is pi n i s refle c ted i n the s e co nda ry status regi ste r at offset 1e h. other tha n this, the pin has n o effect on pci 6254 o peratio n. bpcc_e n i bus/po w e r clock contr o l managem e nt pin. wh e n sign al is tie d high an d the pci 6254 is pla c ed in th e d3h o t power state, the pci 6254 pla c e s the se con dary bu s in the b2 po wer state. th e pci 6254 di sabl es the se con dary clo c ks an d dri v es them to 0 . when tied lo w, placi ng the pci 6254 in the d3h o t power state ha s no effect on the se con dary bu s clo c ks. g p i o [ 3 : 0 ] i o - p u gener a l purpose inpu t o u tpu t pins. these 8 gen eral purp o se si gnal s are prog ram m abl e as eithe r in put-only o r bi-dire c tional sig nals by writin g the gpio output enabl e co ntro l registe r . du ring prst# a s serted, gpi o [3:0] are use d to shift in the clo ck di sabl e se rial d a ta. g p i o [ 7 : 4 ] i o - p u gener a l pur pose inp u t outpu t pins. the s e 4 gen eral pu rpo s e sign als are internally p u l l ed up a n d are p r o g ra mmable as either in put-only or bi - dire ctional sig nals by writin g the gpio output enabl e control re gist er. duri ng n o n - tran spa r e n t mode, gpio [5] can b e enabl ed a s an extern al interrupt so urce on the pri m ary port to trigge r s_int a #. duri ng n o n - tran spa r e n t mode, gpio [4] can b e enabl ed a s an extern al interrupt so urce on the se conda ry port to trigge r p_inta#. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 31 g p i o [ 1 5 : 8 ] i o gener a l pur pose inp u t outpu t pins. the s e 8 gen eral pu rpo s e sign als are prog ram m abl e a s either i nput-o nly o r bi-di r e c tional sig nal s by writing the gpio output enabl e co ntro l registe r . duri ng po we r up reset, the status of the s e pin s are la tched in regi ster xxh for gene ral u s e r defined u s e. they can b e left uncon ne cted if not used . recomme nd use (m ust b e 3.3v input): gpio15: pri m ar y po w e r state : 1 = pri m ary port po wer i s stabl e. gpio14: se c ondar y po w e r state: 1 = secon d a r y port power i s stable. p _ p m e # p t s primar y pm e#: prim ary pci port po wer man age ment event i n terrupt. thi s is u s ed by secon d a r y port devi c e s t o wa ke up primary p o rt host. in tran sp are n t mode, an d in non - tran sp arent with p r i m ary po rt ha s lo wer boot prio rity, p_pme# is always output an d re flect s the st ate of s_pme# input if enabl ed. s _ p m e # p t s seconda r y pme#: second ary pci port powe r man a gement eve n t interru pt. this i s u s ed by primary p o rt devices to wa ke u p seconda ry po rt subsy s tem. in non - t r an spare n t with seco nda ry po rt has l o wer b oot pri o rity, s_pme# is alway s output and refle c ts t he state of p_pme# input if enabled. e e p c l k i o eeprom cl ock. this pi n is the clock si gnal to the eeprom interface use d duri ng autoload an d for vpd functions. thi s pin is three - stated if ee_en# = 1. e e p d a t a i o eeprom serial data. this pin is s e rial data interfac e to the eeprom. this pin i s three-stated if ee_en# = 1. e e _ e n # i eeprom enable. this input shoul d be ?0? to enabl e eeprom use. otherwise it should b e co n nect to logi c ?1? state. 6 4 e n # i - p u 64 bit dev i c e statu s this inp u t h a s no h a rd ware co ntrol function an d is re com m ende d for softwa r e read only as belo w . this status is refle c ted a t registe r 52h bit 4. 0 = po rt use s 64 bit bus. 1 = use 32 bi t bus. t r a n s # i - p d enable tran sparen t mod e : 0 = pci 6254 is config ure d as a stan dard pci-to-p ci bridg e . 1 = pci 6254 is in non - tra n sp are n t mod e . in cpci universal bri dge a pplication s , this ca n be con necte d dire ctl y to the sysen# pin. u_mo d e i - p d enable univ ersal mode : 1 = pci 6254 is config ure d as a unive r sal bridge. test# i-pu 0 = pci 6254 is set to test mode. du rin g normal u s e, the pin shoul d be left unconn ecte d. p v i o i primar y interfac e i/o voltage t h is sig nal must be ti ed to either 3. 3v or 5v, depe nding o n the signali n g voltage of the prima r y interface. s v i o i seconda r y inter f ac e i/o voltage thi s sign al must b e tied to either 3.3v or 5v, dependi n g on the sig n a ling voltage of the second ary interfa c e. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 32 5.9 m u ltiplexed transparent and non-transparent m o de signals n a m e t y p e des c r i p t i o n xb_mem i-pd priv ate dev i ce or cro ss bridge mem o r y space enable : after power up, the function s set by this bit can b e modifi ed by softwa r e at chip con t rol regi ster bit s 2 and 3. this input pin sho u ld not be left unco nne cted . (no n -tr a nsp a rent m o d e ) cros s-bridg e memor y w i ndo w en abl e : when this bit is ?1?, pci 6254 will autom atically claim 16m of memory space. this allo ws the boot up of the lo w prio rit y boot port to move forwa r d without waiting for th e priority boo t port to prog ram the co rre spondi ng mem o ry bar regi sters. although the d e fa ult clai ms 1 6 m , the bar registe r s can be changed by eeprom or software to change t he window size if this pin i s ?1?, the p or s port_ r eady mech ani sm will not be releva nt and acce ss to bar regist er will not be retried. (tran s par e nt mode) priv ate memor y enable: this fun c tion is not availabl e and the inp u t must be se t to 0 during tran sp are n t mode. p_inta# / p_clk r un# pts in non-tra n spare n t and universal mod e , this is prim ary port interrupt output p_inta# . in tran spa r e n t mode, this is primar y clkr u n used by the centra l reso urce to stop the pci clo ck o r to slo w it down. this fun c tion is by default disa bled and ne ed to b e enabl ed by softwa r e. if this feature i s n o t enable d , this pin can b e left uncon ne cted. s_inta# / s_clk r un# pts in non-tra n spare n t mode, this is secon dary po rt interru pt output s_inta# . in tran spa r e n t mode, this is second ar y c l kr un u s ed by the cen t ral resource to s t op the pci c l ock or to s l ow it down. this function is by default disa bled an d need to be e n abled by software. if this feature i s not enabl ed, this pin can b e left uncon n e cted. s_idsel pi seconda r y id select: used as chip sel e ct line for ty pe-0 config uration acce ss to pci 6254 se co n dary co nfigu r ati on sp ace. pin is use d o n ly during non - tra n sparent mode. p_boot i-pu primar y port boot indica tor input: p_boot = 1: primary port ha s bo ot prio rity: primary po rt must set p_port _re a dy bit before secon d a r y port can p r o c eed to boot. p_boot = 0 : seconda ry port has bo o t priority: secon dary port must set s_port _re a dy bit before primar y port can proce e d to boot. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 33 5.10 jtag/boundary scan interface signals n a m e t y p e des c r i p t i o n t c k i - p u test clock : used to clo ck state informa t ion and test data into and out of pci 6254 d u rin g o peratio n of the tap. this pin sho u l d be pulled h i gh or pull ed l o w to a kn own state usi ng an external resi stor. t m s i - p u test mo de select: used t o control the state of the tap controlle r in pci 6254. this pin sho u l d be pulled h i gh or pull ed l o w to a kn own state usi ng an external resi stor. t d o o test data o u tpu t : us ed to s e rially s h ift tes t dat a and test instru cti ons o u t of pci 6254 du ri ng tap operation. t d i i - p u test data input: used to s e rially s h ift tes t data and tes t ins t ruc t ions into pci 6254 d u rin g tap operatio n. this pin sho u l d be pulled h i gh or pull ed l o w to a kn own state usi ng an external resi stor. t r s t # i test res e t: it provides a n asyn chrono u s init ialization of the tap controlle r. this pin m u s t be pulled hi gh or pull ed l o w to a kn own state usi ng an external resi stor. we re co mmend p u llin g low u s ing a 330o hm re si stor. 5.11 power signals n a m e t y p e des c r i p t i o n v d d + 3 . 3 v g n d grou n d pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 34 5.12 pin assignment sorted by location loc a t i o n p i n n a m e a 0 1 v s s a 0 2 v d d a 0 3 s _ a d [ 3 0 ] a 0 4 s _ a d [ 2 7 ] a 0 5 v s s a 0 6 s _ a d [ 2 3 ] a 0 7 s _ a d [ 2 2 ] a 0 8 s _ a d [ 1 9 ] a 0 9 s _ a d [ 1 6 ] a 1 0 s _ t r d y # a 1 1 s _ l o c k # a 1 2 v s s a 1 3 s _ a d [ 1 3 ] a 1 4 s _ m 6 6 e n a 1 5 s _ c b e # [ 0 ] a 1 6 v s s a 1 7 s _ a d [ 0 2 ] a 1 8 s _ a d [ 0 0 ] a 1 9 s _ c b e # [ 7 ] a 2 0 s _ c b e # [ 5 ] a 2 1 s _ a d [ 6 2 ] a 2 2 e e p d a t a a 2 3 e e p c l k b 0 1 v d d b 0 2 v s s b 0 3 s _ a d [ 2 9 ] b 0 4 s _ a d [ 2 6 ] b 0 5 s _ a d [ 2 4 ] b 0 6 s i d s e l b 0 7 s _ a d [ 2 0 ] b 0 8 s _ a d [ 1 8 ] b 0 9 s _ f r a m e # b 1 0 s _ d e v s e l # b 1 1 s _ s e r r # b 1 2 s _ p a r b 1 3 s _ a d [ 1 4 ] b 1 4 s _ a d [ 1 0 ] b 1 5 s _ a d [ 0 8 ] b 1 6 s _ a d [ 0 6 ] b 1 7 s _ a d [ 0 4 ] b 1 8 s _ a d [ 0 1 ] b 1 9 s _ r e q 6 4 # b 2 0 v d d b 2 1 v s s b 2 2 v s s b 2 3 v d d c 0 1 s _ r e q # [ 1 ] c 0 2 s _ r e q # [ 2 ] c 0 3 s _ a d [ 3 1 ] c 0 4 s _ a d [ 2 8 ] c 0 5 s _ a d [ 2 5 ] c 0 6 s _ c b e # [ 3 ] c 0 7 v s s c 0 8 s _ a d [ 1 7 ] c 0 9 s _ i r d y # c 1 0 s _ s t o p # c 1 1 s _ p e r r c 1 2 s _ c b e # [ 1 ] c 1 3 s _ a d [ 1 5 ] c 1 4 s _ a d [ 1 1 ] c 1 5 s _ a d [ 0 9 ] c 1 6 s _ a d [ 0 7 ] c 1 7 s _ a d [ 0 5 ] c 1 8 s _ a c k 6 4 # c 1 9 s _ c b e # [ 6 ] c 2 0 s _ a d [ 6 3 ] c 2 1 s _ a d [ 6 0 ] c 2 2 s _ a d [ 5 8 ] c 2 3 s _ a d [ 5 9 ] d 0 1 s _ r e q # [ 5 ] d 0 2 s _ r e q # [ 6 ] d 0 3 s _ r e q # [ 3 ] d 0 4 s _ r e q # [ 0 ] d 0 5 v d d d 0 6 v d d d 0 7 s _ a d [ 2 1 ] d 0 8 v s s d 0 9 s _ c b e # [ 2 ] d 1 0 v d d d 1 1 v d d d 1 2 v s s d 1 3 s _ a d [ 1 2 ] d 1 4 v d d d 1 5 v d d d 1 6 v s s d 1 7 s _ a d [ 0 3 ] d 1 8 v d d d 1 9 s _ c b e # [ 4 ] d 2 0 s _ a d [ 6 1 ] d 2 1 s _ a d [ 5 7 ] d 2 2 s _ a d [ 5 5 ] d 2 3 x b _ m e m e 0 1 s _ r e q # [ 8 ] e 0 2 s _ g n t # [ 0 ] e 0 3 s _ r e q # [ 7 ] e 0 4 s _ r e q # [ 4 ] e 0 8 s _ p m e # e 0 9 s _ i n t a # e 1 0 n c e 1 1 e j e c t e 1 2 v s s e 1 3 t e s t # e 1 4 v d d e 1 5 s c l k of f e 1 6 v s s e 2 0 s _ a d [ 5 6 ] e 2 1 s _ a d [ 5 4 ] e 2 2 v d d e 2 3 s _ a d [ 5 3 ] f 0 1 s _ g n t # [ 2 ] f 0 2 s _ g n t # [ 3 ] f 0 3 s _ g n t # [ 1 ] f 0 4 v s s f 2 0 v s s f 2 1 s _ a d [ 5 2 ] f 2 2 s _ a d [ 5 0 ] f 2 3 s _ a d [ 5 1 ] g 0 1 s _ g n t # [ 4 ] g 0 2 s _ g n t # [ 6 ] g 0 3 s _ g n t # [ 7 ] g 0 4 s _ g n t # [ 5 ] g 2 0 s _ a d [ 4 9 ] g 2 1 s _ a d [ 4 7 ] g 2 2 s _ a d [ 4 8 ] g 2 3 v s s h 0 1 s _ g n t # [ 8 ] h 0 2 s _ r s t o u t # h 0 3 v s s h 0 4 v d d h 0 5 s _ r s t i n # h 1 9 t r a n s # h 2 0 v d d h 2 1 s _ a d [ 4 4 ] h 2 2 s _ a d [ 4 5 ] h 2 3 s _ a d [ 4 6 ] j 0 1 v d d j 0 2 v s s j 0 3 v d d j 0 4 s _ c l k j 0 5 g p i o 4 j 1 9 u _ m o d e j 2 0 s _ a d [ 4 2 ] j 2 1 v d d j 2 2 s _ a d [ 4 1 ] j 2 3 s _ a d [ 4 3 ] k 0 1 s _ c f n # k 0 2 g p i o [ 0 3 ] k 0 3 g p i o [ 0 2 ] k 0 4 v s s k 0 5 g p i o 5 k 1 0 v s s k 1 1 v s s k 1 2 v s s k 1 3 v s s k 1 4 v s s k 1 9 6 4 e n # k 2 0 v s s k 2 1 s _ a d [ 3 8 ] k 2 2 s _ a d [ 3 9 ] k 2 3 s _ a d [ 4 0 ] l 0 1 g p i o [ 0 ] l 0 2 s _ c l k _ o [ 0 ] l 0 3 s _ c l k _ o [ 1 ] l 0 4 g p i o [ 0 1 ] l 0 5 g p i o 6 l 1 0 v s s l 1 1 v s s l 1 2 v s s l 1 3 v s s l 1 4 v s s l 1 9 v s s l 2 0 v s s l 2 1 s _ a d [ 3 6 ] l 2 2 s _ a d [ 3 5 ] l 2 3 s _ a d [ 3 7 ] m 0 1 s _ c l k _ o [ 3 ] m 0 2 s _ c l k _ o [ 4 ] m 0 3 s _ c l k _ o [ 2 ] m 0 4 v d d m 0 5 g p i o 7 m 1 0 v s s m 1 1 v s s m 1 2 v s s m 1 3 v s s m 1 4 v s s m 1 9 v d d m 2 0 v d d m 2 1 s _ a d [ 3 2 ] m 2 2 s _ a d [ 3 4 ] m 2 3 s _ a d [ 3 3 ] n 0 1 s _ c l k _ o [ 6 ] n 0 2 v s s n 0 3 s _ c l k _ o [ 5 ] n 0 4 v d d n 0 5 v d d n 1 0 v s s n 1 1 v s s n 1 2 v s s n 1 3 v s s n 1 4 v s s n 1 9 s c l k s t b n 2 0 t c k n 2 1 s _ p a r 6 4 n 2 2 s _ v i o n 2 3 t r s t # p 0 1 s _ c l k _ o [ 9 ] p 0 2 s _ c l k _ o [ 8 ] p 0 3 s _ c l k _ o [ 7 ] p 0 4 v s s p 0 5 p r s t o u t # p 1 0 v s s p 1 1 v s s p 1 2 v s s p 1 3 v s s p 1 4 v s s p 1 9 l _ s t a t p 2 0 v s s p 2 1 t m s p 2 2 t d o pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 35 pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 36 p23 tdi r01 vdd r02 p_gnt# r03 p_rstin# r04 bpcce r05 gpio8 r19 enum# r20 p_vio r21 msk_in r22 config66 r23 pwrgd t01 vdd t02 vss t03 p_clkin t04 vdd t05 p_pme# t19 p_boot t20 vdd t21 p_par64 t22 p_ad[32] t23 p_ad[33] u01 p_ad[29] u02 p_ad[31] u03 p_req# u04 p_ad[30] u20 p_ad[35] u21 vss u22 p_ad[34] u23 p_ad[36] v01 p_ad[27] v02 p_ad[28] v03 p_ad[26] v04 vss v20 vss v21 p_ad[39] v22 p_ad[37] v23 p_ad[38] w01 p_ad[24] w02 p_ad[25] w03 vdd w04 p_ad[23] w08 p_inta# w09 gpio9 w10 gpio10 w11 gpio11 w12 vss w13 gpio12 w14 gpio13 w15 gpio14 w16 gpio15 w20 p_ad[44] w21 p_ad[42] w22 p_ad[40] w23 p_ad[41] y01 p_idsel y02 p_cbe#[3] y03 p_ad[22] y04 p_ad[19] y05 p_ad[16] y06 vdd y07 p_serr# y08 vss y09 vss y10 vdd y11 p_ad[08] y12 vss y13 p_ad[01] y14 vdd y15 p_cbe#[5] y16 vss y17 p_ad[59] y18 vdd y19 p_ad[52] y20 p_ad[47] y21 p_ad[45] y22 vdd y23 p_ad[43] a a01 p_ad[21] a a02 vss a a03 p_ad[20] a a04 p_ad[17] a a05 p_frame# a a06 p_devsel# a a07 p_cbe#[1] a a08 p_ad[14] a a09 p_ad[11] a a10 p_ad[09] a a11 p_ad[06] a a12 p_ad[05] a a13 p_ad[02] a a14 p_ad[00] a a15 p_cbe#[7] a a16 p_ad[63] a a17 p_ad[61] a a18 p_ad[56] a a19 p_ad[54] a a20 p_ad[51] a a21 p_ad[48] aa22 eject_en# a a23 p_ad[46] a b01 oscsel# a b02 oscin a b03 p_ad[18] a b04 p_cbe#[2] a b05 p_trdy# a b06 p_lock# a b07 p_par a b08 p_ad[15] a b09 p_ad[12] a b10 p_m66en a b11 p_ad[07] a b12 p_ad[04] a b13 p_ad[03] a b14 p_ack64# a b15 p_cbe#[6] a b16 p_ad[62] a b17 p_ad[60] a b18 p_ad[58] a b19 vdd a b20 p_ad[53] a b21 p_ad[50] a b22 vss a b23 vdd a c01 vss a c02 vdd a c03 vdd a c04 vss a c05 p_irdy# a c06 p_stop# a c07 p_perr# a c08 vdd a c09 p_ad[13] a c10 p_ad[10] a c11 p_cbe#[0] a c12 vdd a c13 vss a c14 p_req64# a c15 p_cbe#[4] a c16 vdd a c17 vss a c18 p_ad[57] a c19 p_ad[55] a c20 vss a c21 p_ad[49] ac22 ee_en# a c23 vss 5.13 pin assignment sorted by pin name loc a t i o n p i n n a m e k 1 9 6 4 e n # r 0 4 b p c c e r 2 2 c o n f i g 6 6 a c 2 2 e e _ e n # a 2 3 e e p c l k a 2 2 e e p d a t a e 1 1 e j e c t aa 2 2 e j e c t _ e n # r 1 9 e n u m # l 0 1 g p i o [ 0 ] l 0 4 g p i o [ 0 1 ] k 0 3 g p i o [ 0 2 ] k 0 2 g p i o [ 0 3 ] w 1 0 g p i o 1 0 w 1 1 g p i o 1 1 w 1 3 g p i o 1 2 w 1 4 g p i o 1 3 w 1 5 g p i o 1 4 w 1 6 g p i o 1 5 j 0 5 g p i o 4 k 0 5 g p i o 5 l 0 5 g p i o 6 m 0 5 g p i o 7 r 0 5 g p i o 8 w 0 9 g p i o 9 p 1 9 l _ s t a t r 2 1 m s k _ i n e 1 0 n c a b 0 2 o s c i n a b 0 1 o s c s e l # a b 1 4 p _ a c k 6 4 # a a 1 4 p _ a d [ 0 0 ] y 1 3 p _ a d [ 0 1 ] a a 1 3 p _ a d [ 0 2 ] a b 1 3 p _ a d [ 0 3 ] a b 1 2 p _ a d [ 0 4 ] a a 1 2 p _ a d [ 0 5 ] a a 1 1 p _ a d [ 0 6 ] a b 1 1 p _ a d [ 0 7 ] y 1 1 p _ a d [ 0 8 ] a a 1 0 p _ a d [ 0 9 ] a c 1 0 p _ a d [ 1 0 ] a a 0 9 p _ a d [ 1 1 ] a b 0 9 p _ a d [ 1 2 ] a c 0 9 p _ a d [ 1 3 ] a a 0 8 p _ a d [ 1 4 ] a b 0 8 p _ a d [ 1 5 ] y 0 5 p _ a d [ 1 6 ] a a 0 4 p _ a d [ 1 7 ] a b 0 3 p _ a d [ 1 8 ] y 0 4 p _ a d [ 1 9 ] a a 0 3 p _ a d [ 2 0 ] a a 0 1 p _ a d [ 2 1 ] y 0 3 p _ a d [ 2 2 ] w 0 4 p _ a d [ 2 3 ] w 0 1 p _ a d [ 2 4 ] w 0 2 p _ a d [ 2 5 ] v 0 3 p _ a d [ 2 6 ] v 0 1 p _ a d [ 2 7 ] v 0 2 p _ a d [ 2 8 ] u 0 1 p _ a d [ 2 9 ] u 0 4 p _ a d [ 3 0 ] u 0 2 p _ a d [ 3 1 ] t 2 2 p _ a d [ 3 2 ] t 2 3 p _ a d [ 3 3 ] u 2 2 p _ a d [ 3 4 ] u 2 0 p _ a d [ 3 5 ] u 2 3 p _ a d [ 3 6 ] v 2 2 p _ a d [ 3 7 ] v 2 3 p _ a d [ 3 8 ] v 2 1 p _ a d [ 3 9 ] w 2 2 p _ a d [ 4 0 ] w 2 3 p _ a d [ 4 1 ] w 2 1 p _ a d [ 4 2 ] y 2 3 p _ a d [ 4 3 ] w 2 0 p _ a d [ 4 4 ] y 2 1 p _ a d [ 4 5 ] a a 2 3 p _ a d [ 4 6 ] y 2 0 p _ a d [ 4 7 ] a a 2 1 p _ a d [ 4 8 ] a c 2 1 p _ a d [ 4 9 ] a b 2 1 p _ a d [ 5 0 ] a a 2 0 p _ a d [ 5 1 ] y 1 9 p _ a d [ 5 2 ] a b 2 0 p _ a d [ 5 3 ] a a 1 9 p _ a d [ 5 4 ] a c 1 9 p _ a d [ 5 5 ] a a 1 8 p _ a d [ 5 6 ] a c 1 8 p _ a d [ 5 7 ] a b 1 8 p _ a d [ 5 8 ] y 1 7 p _ a d [ 5 9 ] a b 1 7 p _ a d [ 6 0 ] a a 1 7 p _ a d [ 6 1 ] a b 1 6 p _ a d [ 6 2 ] a a 1 6 p _ a d [ 6 3 ] t 1 9 p _ b o o t a c 1 1 p _ c b e # [ 0 ] a a 0 7 p _ c b e # [ 1 ] a b 0 4 p _ c b e # [ 2 ] y 0 2 p _ c b e # [ 3 ] a c 1 5 p _ c b e # [ 4 ] y 1 5 p _ c b e # [ 5 ] a b 1 5 p _ c b e # [ 6 ] a a 1 5 p _ c b e # [ 7 ] t 0 3 p _ c l k i n a a 0 6 p _ d e v s e l # a a 0 5 p _ f r a m e # r 0 2 p _ g n t # y 0 1 p _ i d s e l w 0 8 p _ i n t a # a c 0 5 p _ i r d y # a b 0 6 p _ l o c k # a b 1 0 p _ m 6 6 e n a b 0 7 p _ p a r t 2 1 p _ p a r 6 4 a c 0 7 p _ p e r r # t 0 5 p _ p m e # u 0 3 p _ r e q # a c 1 4 p _ r e q 6 4 # r 0 3 p _ r s t i n # y 0 7 p _ s e r r # a c 0 6 p _ s t o p # a b 0 5 p _ t r d y # r 2 0 p _ v i o p 0 5 p r s t o u t # d 2 3 x b _ m e m r 2 3 p w r g d c 1 8 s _ a c k 6 4 # a 1 8 s _ a d [ 0 0 ] b 1 8 s _ a d [ 0 1 ] a 1 7 s _ a d [ 0 2 ] d 1 7 s _ a d [ 0 3 ] b 1 7 s _ a d [ 0 4 ] c 1 7 s _ a d [ 0 5 ] b 1 6 s _ a d [ 0 6 ] c 1 6 s _ a d [ 0 7 ] b 1 5 s _ a d [ 0 8 ] c 1 5 s _ a d [ 0 9 ] b 1 4 s _ a d [ 1 0 ] c 1 4 s _ a d [ 1 1 ] d 1 3 s _ a d [ 1 2 ] a 1 3 s _ a d [ 1 3 ] b 1 3 s _ a d [ 1 4 ] c 1 3 s _ a d [ 1 5 ] a 0 9 s _ a d [ 1 6 ] c 0 8 s _ a d [ 1 7 ] b 0 8 s _ a d [ 1 8 ] a 0 8 s _ a d [ 1 9 ] b 0 7 s _ a d [ 2 0 ] d 0 7 s _ a d [ 2 1 ] a 0 7 s _ a d [ 2 2 ] a 0 6 s _ a d [ 2 3 ] b 0 5 s _ a d [ 2 4 ] c 0 5 s _ a d [ 2 5 ] b 0 4 s _ a d [ 2 6 ] a 0 4 s _ a d [ 2 7 ] c 0 4 s _ a d [ 2 8 ] b 0 3 s _ a d [ 2 9 ] a 0 3 s _ a d [ 3 0 ] c 0 3 s _ a d [ 3 1 ] m 2 1 s _ a d [ 3 2 ] m 2 3 s _ a d [ 3 3 ] m 2 2 s _ a d [ 3 4 ] l 2 2 s _ a d [ 3 5 ] l 2 1 s _ a d [ 3 6 ] l 2 3 s _ a d [ 3 7 ] k 2 1 s _ a d [ 3 8 ] k 2 2 s _ a d [ 3 9 ] k 2 3 s _ a d [ 4 0 ] j 2 2 s _ a d [ 4 1 ] j 2 0 s _ a d [ 4 2 ] j 2 3 s _ a d [ 4 3 ] h 2 1 s _ a d [ 4 4 ] h 2 2 s _ a d [ 4 5 ] h 2 3 s _ a d [ 4 6 ] g 2 1 s _ a d [ 4 7 ] g 2 2 s _ a d [ 4 8 ] g 2 0 s _ a d [ 4 9 ] f 2 2 s _ a d [ 5 0 ] f 2 3 s _ a d [ 5 1 ] f 2 1 s _ a d [ 5 2 ] e 2 3 s _ a d [ 5 3 ] e 2 1 s _ a d [ 5 4 ] d 2 2 s _ a d [ 5 5 ] e 2 0 s _ a d [ 5 6 ] d 2 1 s _ a d [ 5 7 ] c 2 2 s _ a d [ 5 8 ] c 2 3 s _ a d [ 5 9 ] c 2 1 s _ a d [ 6 0 ] d 2 0 s _ a d [ 6 1 ] a 2 1 s _ a d [ 6 2 ] c 2 0 s _ a d [ 6 3 ] a 1 5 s _ c b e # [ 0 ] c 1 2 s _ c b e # [ 1 ] d 0 9 s _ c b e # [ 2 ] c 0 6 s _ c b e # [ 3 ] d 1 9 s _ c b e # [ 4 ] a 2 0 s _ c b e # [ 5 ] c 1 9 s _ c b e # [ 6 ] a 1 9 s _ c b e # [ 7 ] k 0 1 s _ c f n # j 0 4 s _ c l k l 0 2 s _ c l k _ o [ 0 ] l 0 3 s _ c l k _ o [ 1 ] m 0 3 s _ c l k _ o [ 2 ] m 0 1 s _ c l k _ o [ 3 ] m 0 2 s _ c l k _ o [ 4 ] n 0 3 s _ c l k _ o [ 5 ] n 0 1 s _ c l k _ o [ 6 ] p 0 3 s _ c l k _ o [ 7 ] p 0 2 s _ c l k _ o [ 8 ] p 0 1 s _ c l k _ o [ 9 ] b 1 0 s _ d e v s e l # b 0 9 s _ f r a m e # e 0 2 s _ g n t # [ 0 ] f 0 3 s _ g n t # [ 1 ] f 0 1 s _ g n t # [ 2 ] f 0 2 s _ g n t # [ 3 ] g 0 1 s _ g n t # [ 4 ] pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 37 g 0 4 s _ g n t # [ 5 ] g 0 2 s _ g n t # [ 6 ] g 0 3 s _ g n t # [ 7 ] h 0 1 s _ g n t # [ 8 ] e 0 9 s _ i n t a # c 0 9 s _ i r d y # a 1 1 s _ l o c k # a 1 4 s _ m 6 6 e n b 1 2 s _ p a r n 2 1 s _ p a r 6 4 c 1 1 s _ p e r r e 0 8 s _ p m e # d 0 4 s _ r e q # [ 0 ] c 0 1 s _ r e q # [ 1 ] c 0 2 s _ r e q # [ 2 ] d 0 3 s _ r e q # [ 3 ] e 0 4 s _ r e q # [ 4 ] d 0 1 s _ r e q # [ 5 ] d 0 2 s _ r e q # [ 6 ] e 0 3 s _ r e q # [ 7 ] e 0 1 s _ r e q # [ 8 ] b 1 9 s _ r e q 6 4 # h 0 5 s _ r s t i n # h 0 2 s _ r s t o u t # b 1 1 s _ s e r r # c 1 0 s _ s t o p # a 1 0 s _ t r d y # n 2 2 s _ v i o e 1 5 s c l k of f n 1 9 s c l k s t b b 0 6 s i d s e l n 2 0 t c k p 2 3 t d i p 2 2 t d o e 1 3 t e s t # p 2 1 t m s h 1 9 t r a n s # n 2 3 t r s t # j 1 9 u _ m o d e a 0 2 v d d b 0 1 v d d b 2 0 v d d b 2 3 v d d d 0 5 v d d d 0 6 v d d d 1 0 v d d d 1 1 v d d d 1 4 v d d d 1 5 v d d d 1 8 v d d e 1 4 v d d e 2 2 v d d h 0 4 v d d h 2 0 v d d j 0 1 v d d j 0 3 v d d j 2 1 v d d m 0 4 v d d m 1 9 v d d m 2 0 v d d n 0 4 v d d n 0 5 v d d r 0 1 v d d t 0 1 v d d t 0 4 v d d t 2 0 v d d w 0 3 v d d y 0 6 v d d y 1 0 v d d y 1 4 v d d y 1 8 v d d y 2 2 v d d a b 1 9 v d d a b 2 3 v d d a c 0 2 v d d a c 0 3 v d d a c 0 8 v d d a c 1 2 v d d a c 1 6 v d d a 0 1 v s s a 0 5 v s s a 1 2 v s s a 1 6 v s s b 0 2 v s s b 2 1 v s s b 2 2 v s s c 0 7 v s s d 0 8 v s s d 1 2 v s s d 1 6 v s s e 1 2 v s s e 1 6 v s s f 0 4 v s s f 2 0 v s s g 2 3 v s s h 0 3 v s s j 0 2 v s s k 0 4 v s s k 1 0 v s s k 1 1 v s s k 1 2 v s s k 1 3 v s s k 1 4 v s s k 2 0 v s s l 1 0 v s s l 1 1 v s s l 1 2 v s s l 1 3 v s s l 1 4 v s s l 1 9 v s s l 2 0 v s s m 1 0 v s s m 1 1 v s s m 1 2 v s s m 1 3 v s s m 1 4 v s s n 0 2 v s s n 1 0 v s s n 1 1 v s s n 1 2 v s s n 1 3 v s s n 1 4 v s s p 0 4 v s s p 1 0 v s s p 1 1 v s s p 1 2 v s s p 1 3 v s s p 1 4 v s s p 2 0 v s s t 0 2 v s s u 2 1 v s s v 0 4 v s s v 2 0 v s s w 1 2 v s s y 0 8 v s s y 0 9 v s s y 1 2 v s s y 1 6 v s s a a 0 2 v s s a b 2 2 v s s a c 0 1 v s s a c 0 4 v s s a c 1 3 v s s a c 1 7 v s s a c 2 0 v s s a c 2 3 v s s pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 38 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 39 6 configuration registers as a pci bridge, pci 6254 includes the standard type-01h configuration space header defined in bridge 1.1. 6.1 configuration space ma p ? transparent mode superscript legend: 1 = writable when read only register write enable bit is set 2 = eeprom loadable bits 31-24 bits 23-16 bits 15-8 bits 7-0 address 1,2 device id 1,2 vendor id 00h primary status primary command 04h 1,2 class code revision id 08h 1,2 bist 1,2 header type primary latency timer cache line size 0ch reserved 10h ? 17h secondary latency timer subordinate bus number secondary bus number primary bus number 18h secondary status i/o limit i/o base 1ch memory limit memory base 20h prefetchable memory limit prefetchable memory base 24h prefetchable memory base upper 32 bits 28h prefetchable memory limit upper 32 bits 2ch i/o limit upper 16 bits i/o base upper 16 bits 30h reserved ecp pointer 34h reserved 38h bridge control interrupt pin reserved 3ch arbiter control diagnostic control chip control 40h 2 misc options 2 timeout control 2 primary flow through control 44h 2 secondary incremental prefetch count 2 primary incremental prefetch count 2 secondary prefetch line count 2 primary prefetch line count 48h reserved 2 secondary flow through control 2 secondary maximum prefetch count 2 primary maximum prefetch count 4ch reserved test register internal arbiter control 50h eeprom data eeprom address eeprom control 54h reserved 58h-60h pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 40 gpio[3-0] input data gpio[3-0] output enable control gpio[3-0] output data p_serr# event disable 64h clkrun register p_serr# status clock control 68h private memory limit private memory base 6ch private memory base upper 32 bits 70h private memory limit upper 32 bits 74h reserved 78h-98h gpio[7-4] input dataport gpio[7-4] output enable gpio[7-4] output data hot swap switch ror control 9ch gpio[15-8] input dataport gpio[15-8] output enable gpio[15-8] output data pwrup status a0h reserved ac-cch extended register index reserved reserved reserved d0h extended registers dataport d4h reserved d8h 1,2 power management capabilities next item ptr = e4 capability id = 01 dch 1,2 power management data pmcsr bridge support 1, 2 power management csr e0h reserved hscsr = 00 next item ptr = e8 capability id = 06 e4h vpd register = 0000 next item ptr = 00 capability id = 03 e8h vpd data register = 0000_0000 ech reserved f0h-fch 6.2 extended register map 31-24 23-16 15-8 7-0 index 32 bit sticky register 0 0h 32 bit sticky register 1 1h 32 bit sticky register 2 2h 32 bit sticky register 3 3h 32 bit sticky register 4 4h 32 bit sticky register 5 5h 32 bit sticky register 6 6h 32 bit sticky register 7 7h address translation control registers: see following section 8-fh pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 41 6.2.1 address transl ation register map in order to use the address translation functions, the address window set in the bar registers must fall in the range specified in the pci-to-pci bridge standard co nfiguration registers at 20h-2ch for memory base and memory limit or prefetchable memory base and prefetchable memory limit. registers definitions are defined in the non-transparent mode chapter. description of the mechanism is in the address decoding chapter - address translation section . these registers are normally shadowed and can only be ac cessed by setting the downstream translation bar bit at register 9ch. downstream memory 1 bar 14h downstream memory 2 bar or downstream memory 1 bar upper 32 bits 18h these registers are normally shadowed and can only be ac cessed by setting the upstream translation bar bit at register 9ch. upstream i/o or memory 0 bar 10h upstream memory 1 bar 14h upstream memory 2 bar or downstream memory 1 bar upper 32 bits 18h extended registers 31-24 23-16 15-8 7-0 extended register index 2 upstream bar 0 translation address 8h 2 upstream bar 1 translation address 9h 2 upstream bar 2 or upstream bar1 upper 32 bits translation address ah 2 upstream translation enable 2 upstream bar 2 translation mask 2 upstream bar 1 translation mask 2 upstream bar 0 translation mask bh reserved ch 2 downstream bar 1 translation address dh 2 downstream bar 2 or downstream bar1 upper 32 bits translation address eh 2 downstream translation enable 2 downstream bar 2 translation mask 2 downstream bar 1 translation mask 2 downstream bar 0 translation mask fh pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 42 6.3 transparent mode configuration register description 6.3.1 pci standard configuration registers vendor id register (read only) - offset 0h defaults to 3388(h). device id register (read only) - offset 2h defaults to 0020(h) for transparent mode, 21h for non-transparent mode. (note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear) primary command register (read/write) - offset 4h bit function type description 0 i/o space enable r/w controls the bridge?s respons e to i/o accesses on the primary interface. 0=ignore i/o transaction 1=enable response to i/o transaction reset to 0. 1 memory space enable r/w controls the bridge?s response to memory accesses on the primary interface. 0=ignore all memory transaction 1=enable response to memory transaction reset to 0. 2 bus master enable r/w controls the bridge?s ability to operate as a master on the primary interface. 0=do not initiate transaction on the primary interface and disable response to memory or i/o tran sactions on secondary interface 1=enable the bridge to operate as a master on the primary interface reset to 0. 3 special cycle enable r/o no special cycle implementation (set to ?0?). 4 memory write and invalidate enable r/o memory write and invalidate not supported (set to ?0?). 5 vga palette snoop enable r/w controls the bridge?s response to vga compatible palette accesses. 0=ignore vga palette accesses on the primary interface 1=enable response to vga palette writes on the primary interface (i/o address ad[9:0]=3c6h, 3c8h and 3c9h) reset to 0. 6 parity error enable r/w controls the bridge?s response to parity errors. 0=ignore any parity errors 1=normal parity checking performed reset to 0. 7 wait cycle control r/w pci 6254 performs address / data stepping (reset to ?1?). pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 43 8 p_serr# enable r/w controls the enable for the p_serr# pin. 9 fast back to back enable r/w controls the bridge?s ability to generate fast back-to-back transactions to different devices on the primary interface. 0=no fast back to back transaction 1=reserved. pci 6254 does not generate fast back to back cycle. reset to 0. 10-15 reserved r/o reserved. reset to 0. primary status register(read/write) ? offset 6h bit function type description 0-3 reserved r/o reserved (set to ?0?s). 4 ecp r/o enhanced capabilities port. reads as 1 to indicate pci 6254 supports an enhanced capabilities list. 5 66mhz r/o reflects the state of cfg66 input pin. 1 = pci 6254 is 66mhz capable. 6 udf r/o no user-definable features (set to ?0?). 7 fast back to back capable r/o fast back-to-back write capable on primary side (set to ?1?). 8 data parity error detected r/wc it is set when the following conditions are met: 1. p_perr# is asserted bit 6 of command register is set reset to 0. 9-10 devsel timing r/o devsel# timing. reads as 01b to indicate pci 6254 responds no slower than with medium timing 11 signaled target abort r/wc should be set (by a target devic e) whenever a target abort cycle occurs. reset to 0. 12 received target abort r/wc set to ?1? (by a master device) when transactions are terminated with target abort. reset to 0. 13 received master abort r/wc set to ?1? (by a master) when transactions are terminated with master abort. reset to 0. 14 signaled system error r/wc should be set whenever p_serr# is asserted. reset to 0. 15 detected parity error r/wc should be set whenever a parity error is detected regardless of the state of the bit 6 of command register. reset to 0. revision id register (read only) ? offset 8h defaults to 04h. class code register (read only) ? offset 9h defaults to 060400h for transparent mo de, 068000 for non-transparent mode. cache line size register (read/write) ? offset 0ch this register is used when terminating memory write and invalidate transactions. memory read prefetching is controlled by the prefetch count registers. only cache line sizes (in units of 32-bits words) which are power of two are valid. resets to 0. primary latency timer register (read/write) ? offset 0dh this register sets the value for master latency time r which starts counting when the master asserts frame#. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 44 header type register (read only) ? offset 0eh defaults to 1 in transparent mode, 0 in non-transparent mode. bist register (read only) ? offset 0fh this register can be written to by enabling the ror wri te enable bit at register 9ch bit 7. reset to 0. primary bus number register (read/write) ? offset 18h programmed with the number of the pci bus to which the pr imary bridge interface is connected. this value is set with configuration software. reset to 0. secondary bus number register (read/write) ? offset 19h programmed with the number of the pci bus to which the secondary bridge interface is connected. this value is set with configuration software. reset to 0. subordinate bus number register (read/write) ?offset 1ah programmed with the number of the pci bus with the highe st number that is subordinate to the bridge. this value is set with configuration software. reset to 0. secondary latency timer (read/write) ? offset 1bh this register is programmed in units of pci bus clocks. re set to 0. the latency timer checks for master accesses on the secondary side that remain unclaimed by any target. i/o base register (read/write) ? offset 1ch this register defines the bottom addres s of the i/o address range for the bridge. the upper four bits define the bottom address range used by the chip to determine when to forward i/o transactions from one interface to the other. these 4 bits correspond to addr ess bits <15:12> and are writeable. the upper 16 bits corresponding to address bits <31:16> are defined in the i/o base address upper 16 bits register. the address bits <11:0> are assumed to be 000h. the lower four bits (3:0) of this re gister set to ?0001? (read-only) to indicate 32-bit i/o addressing. reset to 0. i/o limit register (read/write) ? offset 1dh this register defines the top address of the i/o address range for the bridge. the upper four bits define the top address range used by the chip to determine when to forward i/o transactions from one interface to the other. these 4 bits correspond to address bits <15:12> and ar e writeable. the upper 16 bits corresponding to address bits <31:16> are defined in the i/o limit address upper 16 bits register. the address bits <11:0> are assumed to be fffh. the lower four bits (3:0) of this register set to ?0001? (read-only) to indicate 32-bit i/o addressing. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 45 secondary status register (read/write) ? offset 1eh bit function type description 0-4 reserved r/o reserved (set to ?0?s). 5 66mhz r/o defaults to 1. pci 6254 is 66mhz capable. 6 udf r/o no user-definable features (set to ?0?). 7 fast back to back capable r/o fast back-to-back write capable on secondary port (set to ?1?). 8 data parity error detected r/wc it is set when the following conditions are met: 1. sperr# is asserted 2. bit 6 of command register is set reset to 0. 9-10 devsel timing r/o medium devsel# timing (set to ?01?) 11 signaled target abort r/wc should be set (by a target devic e) whenever a target abort cycle occurs. should be ?0? after reset. reset to 0. 12 received target abort r/wc set to ?1? (by a master device) when transactions are terminated with target abort. reset to 0. 13 received master abort r/wc set to ?1? (by a master) when transactions are terminated with master abort. reset to 0. 14 received system error r/wc should be set whenever sserr# is detected. should be a ?0 after reset. reset to 0. 15 detected parity error r/wc should be set whenever a parity error is detected regardless of the state of the bit 6 of command register. reset to 0. memory base register (read/write) ? offset 20h this register defines the base addr ess of the memory-mapped address rang e for forwarding the cycle through the bridge. the upper twelve bits corresponding to address bits <31:20> are writeable. the lower 20 address bits (19:0) are assumed to be 00000h. the 12 bits are reset to 0. the lower 4 bits are read only and set to 0. memory limit register (read/write) ? offset 22h this register defines the upper limit address of th e memory-mapped address range for forwarding the cycle through the bridge. the upper twelve bits corresponding to address bits <31:20> are writeable. the 12 bits are reset to 0. the lower 4 bits are read only and are set to 0. the lower 20 address bits (19:0) are assumed to be fffffh. reset to 0. prefetchable memory base register (read/write) - offset 24h this register defines the base add ress of the prefetchable memory-m apped address range for forwarding the cycle through the bridge. the upper twelve bits corres ponding to address bits <31:20> are writeable. the 12 bits are reset to 0. the lower 4 bits are read only and are set to 0. the lower 20 address bits (19:0) are assumed to be 00000h. reset to 0. prefetchable memory limit register (read/write) ? offset 26h this register defines the upper limit address of th e memory-mapped address range for forwarding the cycle through the bridge. the upper twelve bits correspond to address bits <31:20> are writeabl e. the 12 bits are reset to 0. the lower 4 bits are read only and are set to 0. the lower 20 address bits (19:0) are assumed to be fffffh. reset to 0. prefetchable memory base register upper 32 bits (read/write) ? offset 28h this register defines the upper 32 bit <63:32> memo ry base address of the pr efetchable memory-mapped address for forwarding the cycle thr ough the bridge. reset to 0. prefetchable memory limit register upper 32 bits (read/write) ? offset 2ch pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 46 this register defines the upper 32 bit <63:32> memory limit address of the prefetchable memory-mapped address for forwarding the cycle through the bridge. reset to 0. i/o base address upper 16 bits regi ster (read/write) ? offset 30h this register defines the upper 16 bits of a 32-bit ba se i/o address range used for forwarding the cycle through the bridge. reset to 0. i/o limit address upper 16 bits register (read/write) ? offset 32h this register defines the upper 16 bits of a 32-bit limit i/o address range used for forwarding the cycle through the bridge. reset to 0. ecp pointer (read/only) ? offset 34h bit function type description 7-0 ecp pointer r/o enhanced capabilities port o ffset pointer. this register reads as dch to indicate the offset of the power management registers. interrupt pin register (read only) ? offset 3dh reads as 0 to indicate that pci 6254 does not use any interrupt pin. bridge control register (read/write) ? offset 3eh bit function type description 0 parity error response enable r/w controls the bridge?s response to parity errors on the secondary interface. 0=ignore address and data parity errors on the secondary interface 1=enable parity error reporting and detection on the secondary interface reset to 0. 1 s_serr# enable r/w controls the forwarding of s_ serr# to the primary interface. 0=disable the forwarding s_serr# to primary 1=enable the forwarding of s_serr# to primary reset to 0. 2 isa enable r/w controls the bridge?s resp onse to isa i/o addresses, which is limited to the first 64k. 0=forward all i/o addresses in the range defined by the i/o base and i/o limit registers 1=block forwarding of isa i/o addr esses in the range defined by the i/o base and i/o limit registers that are in the first 64k of i/o space that address the last 768 bytes in each 1kbytes block. secondary i/o transactions are forwarded upstream if the address falls within the last 768 bytes in each 1kbytes block there is an isa enable control bit write protect mechanism control by eeprom. when the isa enable control bit write protect bit is set in the eeprom and eeprom initialization is enabled, pci 6254 will change this bit to read only and isa enable feature will not be available. reset to 0. 3 vga enable r/w controls the bridge?s response to vga compatible addresses. 0=do not forward vga compatible memory and i/o addresses from primary to secondary 1=forward vga compatible memory and i/o address from primary to secondary regardless of other settings reset to 0. 4 reserved r/o reserved (set to 0). 5 master abort r/w controls the brid g e behavior in res p ondin g to master aborts on pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 47 mode secondary interface 0=do not report master aborts (r eturn ffff_ffffh on reads and discards data on writes) 1=report master aborts by signaling target abort reset to 0. note: during lock cycles, pci 6254 ignores this bit, and always completes the cycle as a target abort. 6 secondary reset r/w forces the assertion of s_rs tout# signal pin on the secondary interface. 0=do not force the assertion of s_rstout# pin 1=force the assertion of s_rstout# pin reset to 0. 7 fast back to back enable r/w controls the bridge?s ability to generate fast back-to-back transactions to different devices on the secondary interface. 0 = no fast back to back transaction 1= reserved. pci 6254 does not generate fast back to back cycle. reset to 0. 8 primary master timeout r/w sets the maximum number of pci clock for an initiator on the primary bus to repeat the delayed transaction request. 0=timeout after 2 15 pci clocks 1=timeout after 2 10 pci clocks reset to 0. 9 secondary master timeout r/w sets the maximum number of pci clock for an initiator on the secondary bus to repeat the delayed transaction request. 0=timeout after 2 15 pci clocks 1=timeout after 2 10 pci clocks reset to 0. 10 master timeout status r/wc set to ?1? when either primary master timeout or secondary master timeout. reset to 0. 11 master timeout p_serr# enable r/w enable p_serr# assertion during master timeout. 0=p_serr# not asserted on master timeout 1=p_serr# asserted on either primary or secondary master timeout. reset to 0. 15-12 reserved r/o reserved pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 48 chip control register (read/write) ? offset 40h bit function type description 0 reserved r/o 1 memory write disconnect control r/w controls when the chip as a target disconnects memory transactions. when 0, disconnects on queue full or on a 4kb boundary. when 1, disconnects on a cache line boundary, as well as when the queue fills or on a 4 kb boundary. reset value is 0. 2 private or cross bridge memory enable r/w (transparent mode) 1 = enable private memory block reserved only for secondary memory space. the memory space can be programmed using the private memory base/limit registers. if limit is smaller than base, the private memory space is disabled. primary port cannot access this memory space through the bridge and the secondary port will not respond to any memory cycles addressing this private memory space. (in addition in rev aa, the cross-bridge memory window, default at 0-16m space and programmable later by software, is also treated as a private memory block in transparent mode.) (non-transparent mode) cross-bridge memory window enable: when this bit is ?1?, pci 6254 will automatically claim 16m of memory space. this allows the boot up of the low priority boot port to move forward without waiting for the priority boot port to program the corresponding memory bar registers. if this bit is ?1?, the primary or secondary port_ready mechanism will not be relevant and access to bar regi sters will not be retried. although the default claims 16m, the bar registers can be changed by eeprom or software to change the window size. in both transparent and non-transparent modes, this bit resets to the value as presented at the xb_mem input pin. after reset, this bit can be reprogrammed. 3 reserved r/o 4 secondary bus prefetch disable r/w controls pci 6254?s ability to pref etch during upstream memory read transactions. when 0 the chip prefetches and does not forward byte enable bits during memory read transactions. when 1, pci 6254 requests only one dword from the target during memory read transactions and forwards read enable bits. pci 6254 returns a target disconnect to the requesting master on the first data transfer. memory read line and memory read multiple transactions are still prefetchable. reset to 0. 5 live insertion mode r/w enables hardware control of transaction forwarding in the pci 6254. when 0, pin gpio[3] has no effect on the i/o, memory, and master enable bits. when 1, if gpio[3] is set as input, and gpio[3] is driven high, i/o, memory and master enable bits are disabled. 7:6 reserved r/o reserved (set to 0). pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 49 diagnostic control register (read/write) ? offset 41h bit function type description 0 chip reset r/w chip and secondary bus reset. setting this bit will do a chip reset, without asserting s_rstout# and forcing secondary reset bit in bridge control register to be set. a fter resetting all bits except for the secondary reset bit in bridge control register, this bit will be cleared. write 0 has no effect. 2:1 test mode r/w reserved 3 reserved r/w reserved (set to 0). 7:4 reserved r/o reserved (set to 0). arbiter control register (read/write) ? offset 42h bit function type description 8-0 arbiter control r/w each bit controls whet her a secondary bus master is assigned to the high priority group or the low priority group. bits <8:0> correspond to request inputs s_req#[8:0], resp ectively. reset value is 0. 9 pci 6254 priority r/w defines whether the secondary port of pci 6254 is in high priority group or the low priority group. reset to 1. 0=low priority group 1=high priority group . 11:10 reserved r/o reserved (set to ?0?s) 12 primary port ordering rule r/w reserved (default and should be set to ?0?) 13 secondary port ordering rule r/w reserved (default and should be set to ?0?) 14 upstream 64 bit cycle control r/w reserved (default and should be set to ?0?) 15 downstream 64 bit cycle control r/w reserved (default and should be set to ?0?) pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 50 primary flow through control register - offset 44h bit function type description 2-0 primary posted write completion wait count r/w maximum number of clocks that pci 6254 will wait for posted write data from initiator if delivering write data in flow through mode and internal post write queues are almost empty. if the count is exceeded without any additional data from the initiator, the cycle to target will be terminated to be completed later. 000 : pci 6254 will terminate cycle if there is only 1 data entry left in the internal write queue. 001 : pci 6254 will deassert irdy#, and wait 1 clock for data before terminating cycle. ? 111 : pci 6254 will wait 7 clocks for source data. 3 reserved r/o reserved. returns 0 when read 6-4 primary delayed read completion wait count maximum number of clocks that pci 6254 will wait for delayed read data from target if returning read data in flow through mode and internal delayed read queue is almost full. if the count is exceeded without any additional space in the qu eue, the cycle to target will be terminated, and completed when initiato r retries the rest of the cycle. 000 : pci 6254 will terminate cycle if only 1 data entry is left in the read queue. 001 : pci 6254 will deassert trdy#, and wait 1 clock for data before terminating cycle. ? 111 : pci 6254 will wait 7 clocks for source data. 7 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 51 timeout control register - offset 45h bit function type description 2-0 maximum retry counter control r/w controls maximum number of times that pci 6254 will retry a cycle before signaling a timeout. this timeout applies to read/write retries and can be enabled to trigger serr# on the primary or secondary port depending the serr# ev ents that are enabled. maximum number of retries to timeout = 0000 : 2 24 0001 : 2 18 0010 : 2 12 0011 : 2 6 0111 : 2 0 reset to 0. 3 reserved r/o 5:4 primary master timeout divider r/w provides an additional option for the primary master timeout. timeout counter can optionally be divided by 256, in addition to its original setting in the bridge control register. original setting is 32k by default and programmable to 1k. 11 : timeout counter = primary master timeout / 256 10 : timeout counter = primary master timeout / 16 01 : timeout counter = primary master timeout / 8 00: counter = primary master timeout / 1 defaults to 0 7:6 secondary master timeout divider r/w provides an additional option for the secondary master timeout. timeout counter can optionally be divided by 256, in addition to its original setting in the bridge control register. original setting is 32k by default and programmable to 1k. 11 : timeout counter = primary master timeout / 256 10 : timeout counter = primary master timeout / 16 01 : timeout counter = primary master timeout / 8 00: counter = primary master timeout / 1 defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 52 miscellaneous options - offset 46h bit function type description 0 write completion wait for perr# r/w if 1, pci 6254 will always wait fo r perr# status of the target before completing a delayed write transaction to the initiator. defaults to 0 1 read completion wait for par r/w if 1, pci 6254 will always wait for par status of the target before completing a delayed read transaction to the initiator. defaults to 0 2 dtr out of order enable r/w if 1, pci 6254 may return delayed read transactions in a different order than requested. otherwise , delayed read transactions are returned in the same order as requested defaults to 0 3 generate parity enable r/w if 1, pci 6254 as a master will generate the par and par64 to cycles going across the bridge, otherwise, pci 6254 passes along the par/par64 of the cycle as stored in the internal buffers. defaults to 0 6-4 address step control r/w during configuration type 0 cy cles, pci 6254 will drive the address for the number of clocks specified in this register before asserting frame#. 000 : pci 6254 will assert frame# at the same time as the address. 001 : pci 6254 will assert frame# 1 clock after it drives the address on the bus. ? 111 : pci 6254 will assert frame# 7 clocks after it drives the address on the bus. 8-7 reserved r/w defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 53 9 prefetch early termination r/w if 1, pci 6254 will terminate pref etching at the current calculated count if flowthrough is not yet achieved, and another prefetchable read cycle is accepted by the pci 6254. if 0, pci 6254 will always finish prefetching as programmed at the prefetch count registers, regardless of any other outstanding prefetchable reads in the transaction queue. 10 read minimum enable r/w if 1, pci 6254 will only initiate read cycles if there is available space in the fifo as specified by t he prefetch count registers. 15,11 force 64 bit control r/w if set, 32-bit prefetchable reads or 32-bit posted memory write cycles on one side will be converted to 64- bit cycles on completion to target side if target supports 64-bit tran sfers. if set to 0, cycles are not converted. when combined with the control of bit 15 of this register, the following control is provided: (bit 15 is set to 0 for rev aa and cannot be changed) bit 15, 11 0, 0 disable (default) 0, 1 convert to 64 bit command onto both ports 1, 0 convert to 64 bit command onto secondary port 1, 1 convert to 64 bit command onto primary port starting address for all cycles using this feature should be on the qword boundary. defaults to 0 12 memory write and invalidate control r/w if 1, pci 6254 will pass memory write and invalidate commands if there is at least 1 cache line of fi fo space available, otherwise it will complete as a memory write cycle. if 0, pci 6254 will retry memory write and invalidate commands if there is no space for 1 cacheline of data in the internal queues. defaults to 0 13 primary lock enable r/w if 1, pci 6254 will follow the lock protocol on the primary interface. otherwise, lock is ignored. defaults to 0 (rev aa defaults to 1) 14 secondary lock enable r/w if 1, pci 6254 will follow the lock protocol on the secondary interface. otherwise, lock is ignored. defaults to 0 15,11 force 64 bit control r/w see description in bit 11 section. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 54 6.3.2 prefetch control registers registers 44h, 48h ? 4dh are the pref etch control registers, and are used to fine-tune memory read prefetch behavior of the pci 6254. detailed descriptions of thes e registers can be found in chapter 18 flow through optimization. primary initial prefetch count - offset 48h bit function type description 5-0 primary initial prefetch count r/w controls initial prefetch count on the primary bus during reads to prefetchable memory space. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. secondary initial prefetch count - offset 49h bit function type description 5-0 secondary initial prefetch count r/w controls initial prefetch count on the secondary bus during reads to prefetchable memory space. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. primary incremental prefetch count - offset 4ah bit function type description 5-0 primary incremental prefetch count r/w controls incremental read prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge will prefetch an additional ?primary incremental prefetch count? dwords. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. this register value must not exceed half the value programmed in the primary maximum prefetch count register. otherwise, no incremental prefetch will be performed. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 55 secondary incremental prefetch count - offset 4bh bit function type description 5-0 secondary incremental prefetch count r/w this controls incremental r ead prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge will prefetch an additional ?secondary incremental prefetch count? dwords. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. this register value must not exceed half the value programmed in the secondary maximum prefetch count register. otherwise, no incremental prefetch will be performed. defaults to 10h 7-6 reserved r/o reserved. returns 0 when read primary maximum prefetch count - offset 4ch bit function type description 5-0 primary maximum prefetch count r/w this value limits the cumulative maximum count of prefetchable dwords that are allocated to one entry on the primary when flow through for that entry was not achieved. this register value should be an even number. bit 0 is read only and is always 0. exception: 0h = 256 bytes = maximum programmable count defaults to 20h 7-6 reserved r/o reserved. returns 0 when read secondary maximum prefetch count - offset 4dh bit function type description 5-0 secondary maximum prefetch count r/w register limits the cumulative maximum count of prefetchable dwords that are allocated to one entry on the secondary when flow through for that entry was not achieved. this register value should be an even number. bit 0 is read only and is always 0. exception: 0h = 256 bytes = maximum programmable count defaults to 20h 7-6 reserved r/o reserved. returns 0 when read pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 56 secondary flow through control register - offset 4eh bit function type description 2-0 secondary posted write completion wait count r/w maximum number of clocks that pci 6254 will wait for posted write data from initiator if delivering write data in flow through mode and internal post write queues are al most empty. if the count is exceeded without any additional data from the initiator, the cycle to target will be terminated, to be completed later. 000 : pci 6254 will terminate cycle if there is only 1 data entry left in the internal write queue. 001 : pci 6254 will deassert irdy#, and wait 1 clock for data before terminating cycle. ? 111 : pci 6254 will wait 7 clocks for source data. 3 reserved r/o reserved. returns 0 when read 6-4 secondary delayed read completion wait count maximum number of clocks that pci 6254 will wait for delayed read data from target if returning read data in flow through mode and internal delayed read queue is almost full. if the count is exceeded without any additional space in the qu eue, the cycle to target will be terminated, and completed when initiato r retries the rest of the cycle. 000 : pci 6254 will terminate cycle if only 1 data entry is left in the read queue. 001 : pci 6254 will deassert trdy#, and wait 1 clock for data before terminating cycle. ? 111 : pci 6254 will wait 7 clocks for source data. 7 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 57 internal arbiter control register - offset 50h bit function type description 0 low priority group fixed arbitration r/w if 1, the low priority group uses the fixed priority arbitration scheme, otherwise a rotating priority arbitration scheme is used defaults to 0 1 low priority group arbitration order r/w this bit is only valid when the low priority arbitration group is set to a fixed arbitration scheme. if 1, priority decreases in ascending numbers of the master, for example master #4 will have higher priority than master #3. if 0, the reve rse is true. this order is relative to the master with the highest priority for this group, as specified in bits 7-4 of this register. defaults to 0 2 high priority group fixed arbitration r/w if 1, the high priority group uses the fixed priority arbitration scheme, otherwise a rotating priority arbitration scheme is used defaults to 0 3 high priority group arbitration order r/w this bit is only valid when the high priority arbitration group is set to a fixed arbitration scheme. if 1, priority decreases in ascending numbers of the master, for example master #4 will have higher priority than master #3. if 0, the reve rse is true. this order is relative to the master with the highest priority for this group, as specified in bits 11-8 of this register. defaults to 0 7-4 highest priority master in low priority group r/w controls which master in the low priority group has the highest priority. it is valid only if the gr oup uses the fixed arbitration scheme. 0000 : master#0 has highest priority 0001 : ? 1001 : pci 6254 has highest priority 1010-1111 : reserved defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 58 11-8 highest priority master in high priority group r/w controls which master in the high priority group has the highest priority. it is valid only if the gr oup uses the fixed arbitration scheme. 0000 : master#0 has highest priority 0001 : ? 1001 : pci 6254 has highest priority 1010-1111 : reserved defaults to 0 12-15 bus parking control r/w controls bus grant behavior during idle. 0000 : last master granted is parked 0001 : master #0 is parked ? 1001 : master #8 is parked 1010 : pci 6254 is parked other : grant is deasserted defaults to 0 pci 6254 test register ? offset 52h bit function type description 0 eeprom autoload control r/w if 1, disables eeprom autoload. this is a testing feature only. in order to stop eeprom load in transparent mode, 1 must be written into this register within 1200 clocks after p_rstin# goes high. in non-transparent mode, 1 must be written into this register within 1200 clocks after pwrgd goes high. 1 fast eeprom autoload r/w if 1, speeds up eeprom autoload by 32 times. this is a testing feature only. in order to enable fast eeprom load in transparent mode, 1 must be written into this register within 1200 clocks after p_rstin# goes high. in non- transparent mode, 1 must be written into this register within 1200 clocks after pwrgd goes high. 2 eeprom autoload status r/o status of eeprom autoload. 3 reserved r/o reserved 4 64en# r/o reflects the 64en# pin status 5 s_cfn# r/o reflects the s_cfn# pin status 6 trans# r/o reflects the trans# pin status 7 u_mode r/o reflects the u_mode pin status pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 59 eeprom control - offset 54h bit function type description 0 start r/w starts the eeprom read or write cycle. 1 eeprom command r/w controls the command sent to the eeprom 1 : write 0 : read 2 eeprom error r/o this bit is set to 1 if eeprom ack was not received during eeprom cycle. 3 eeprom autoload successful r/o this bit is set to 1 if eeprom autoload occurred su ccessfully after reset, and some configuration regi sters were loaded with values programmed in the eeprom. if zero, eeprom autoload was unsuccessful or was disabled. 5-4 reserved r/o reserved. returns ?0? when read. 7-6 eeprom clock rate r/w controls frequency of eeprom clock. eeprom clock is derived from the primary pci clock. 00 = pclk/1024 01 = pclk/512 10 = pclk/256 11 = pclk/32 (for test mode use) defaults to 10 (pci 6254 rev aa defaults to 00). eeprom address - offset 55h bit function type description 0 reserved r/o starts the eeprom read or write cycle. 7-1 eeprom address r/w word address for eeprom cycle. eeprom control - offset 56h bit function type description 15-0 eeprom data r/w contains data to be written to the eeprom. during reads, this register contains data received fr om the eeprom after a read cycle has completed. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 60 p_serr# event disable register - offset 64h bit function type description 0 reserved r/o reserved. returns 0 when read 1 posted write parity error r/w controls ability of pci 6254 to assert p_serr# when a data parity error is detected on the target bus during a posted write transaction. p_serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 2 posted memory write nondelivery r/w controls ability of pci 6254 to assert p_serr# when it is unable to deliver posted write data after 2 (or programmed maximum retry count at timeout control register) attempts. p_serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. 24 reset value is 0. 3 target abort during posted write r/w controls ability of pci 6254 to assert p_serr# when it receives a target abort when attempting to deliver posted write data. p_serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 4 master abort on posted write r/w controls ability of pci 6254 to assert p_serr# when it receives a master abort when attempting to deliver posted write data. p_serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 5 delayed configuration or io write nondelivery r/w controls ability of pci 6254 to assert p_serr# when it is unable to deliver delayed write data after 2 24 (or programmed maximum retry count at timeout control register) attempts. p_serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 6 delayed read- no data from target r/w controls ability of pci 6254 to assert p_serr# when it is unable to transfer any read data from the target after 2 24 (or programmed maximum retry count at timeout control register) attempts. p_serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 7 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 61 gpio[3:0] output data register - offset 65h bit function type description 3:0 gpio[3:0] output write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit low on the gpio[3:0] bus if it is programmed as output. writing 0 has no effect. read returns the last written value. resets to 0. 7:4 gpio[3:0] output write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit high on the gpio[3:0] bus if it is programmed as output. writing 0 has no effect. read returns the last written value. resets to 0. gpio [3:0] output enable register - offset 66h bit function type description 3:0 gpio output enable write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[3:0] bus as input only. writing 0 has no effect. read returns the last value written. resets to 0. 7:4 gpio output enable write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[3:0] bus as output. gpio[3:0] then drives the value set in the output data register (reg 65h). writing 0 has no effect. read returns the last written value. resets to 0. gpio [3:0] input data register - offset 67h bit function type description 3:0 reserved r/o reserved 7:4 gpio[3:0] input data r/o this read-only register reads t he state of the gpio[3:0] pins. the state is updated on the pci clock cycle following a change in the gpio[3:0] state. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 62 clock control register (read/write) ? offset 68h bit function type description 1:0 clock 0 disable r/w if either bit is 0, s_clkout[0] is enabled. when both bits are 1, s_clkout[0] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 0. 3:2 clock 1 disable r/w if either bit is 0, s_clko[1] is enabled. when both bits are 1, s_clko[1] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 1. 5:4 clock 2 disable r/w if either bit is 0, s_clko[2] is enabled. when both bits are 1, s_clko[2] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 2. 7:6 clock 3 disable r/w if either bit is 0, s_clko[3] is enabled. when both bits are 1, s_clko[3] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 3. 8 clock 4 disable r/w if 0, s_clko[4] is enabled. when 1, s_clko[4] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 9 clock 5 disable r/w if 0, s_clko[5] is enabled. when 1, s_clko[5] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 10 clock 6 disable r/w if 0, s_clko[6] is enabled. when 1, s_clko[6] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 11 clock 7 disable r/w if 0, s_clko[7] is enabled. when 1, s_clko[7] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 63 12 clock 8 disable r/w if 0, s_clko[8] is enabled. when 1, s_clko[8] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 13 clock 9 disable r/w if 0, s_clko[9] is enabled. when 1, s_clko[9] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 15-14 reserved r/o reserved p_serr# status register (read/write) ? offset 6ah bit function type description 0 address parity error r/wc signal p_serr# was asserted due to address parity error on either side of the bridge. reset to 0. 1 posted write data parity error r/wc signal p_serr# was asserted due to a posted write data parity error on the target bus. reset to 0. 2 post write nondelivery r/wc signal p_serr# was asserted because pci 6254 was unable to deliver posted write data to t he target before timeout counter expires. reset to 0. 3 target abort during posted write r/wc signal p_serr# was asserted because pci 6254 received a target abort when delivering posted write data. reset to 0. 4 master abort during posted write r/wc signal p_serr# was asserted because pci 6254 received a master abort when delivering posted write data. reset to 0. 5 delayed write nondelivery r/wc signal p_serr# was asserted because pci 6254 was unable to deliver delayed write data before time -out counter expires. reset to 0. 6 delayed read failed r/wc signal p_serr# was asserted because pci 6254 was unable to read any data from the target be fore time-out counter expires. reset to 0. 7 delayed transaction master timeout r/wc signal p_serr# was asserted because a master did not repeat a read or write transaction before the master timeout counter expired on the initiator?s bus. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 64 clkrun register (read/write) ? offset 6bh bit function type description 0 secondary clock stop status r/w secondary clock stop status 0 = secondary clock not stopped 1 = secondary clock stopped defaults to 0 1 secondary clkrun enable r/w secondary clkrun protocol enable 0 = disable 1 = enable defaults to 0 2 primary clock stop r/w primary clock stop 0 = allow primary clock to stop if secondary clock is stopped 1 = always keep primary clock running defaults to 0 3 primary clkrun enable r/w primary clkrun protocol enable 0 = disable 1 = enable defaults to 0 4 clkrun mode r/w clkrun mode 0 = stop the secondary clock only on request from the primary bus 1 = stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus. defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 65 6.3.3 private memory private memory can be enabled via chip control re gister bit 2 or by using the xb_mem input pin. private memory base register (read/write) ? offset 6ch this register defines the base addr ess of the private memory address ra nge. the upper twelve bits corresponding to address bits <31:20> are writeable. the lower 20 addres s bits (19:0) are assumed to be 00000h. the 12 bits are reset to 0. the lower 4 bits are read only and set to b?0001?. private memory limit register (read/write) ? offset 6eh this register defines the upper limit address of the private memory addr ess range. the upper twelve bits corresponding to address bits <31:20> are writeable. the 12 bits are reset to 0. the lower 4 bits are read only and are set to 0. the lower 20 address bits (19:0) are assumed to be fffffh. reset to b?0001?. private memory base register upper 32 bits (read/write) ? offset 70h this register defines the upper 32 bit <63:32> memory bas e address of the private memo ry address. reset to 1. private memory limit register upper 32 bits (read/write) ? offset 74h this register defines the upper 32 bit <63:32> memory lim it address of the private memo ry address. reset to 0. hot swap switch and ror control (r/w) ? offset 9ch bit function type description 0 hot swap extraction switch r/w hot swap extraction switch: software switch used to signal extraction of board. if set, board is in inserted state. writing a ?0? to this bit will signal the pending extraction of the board. 4-1 reserved r/o reserved 5 downstream translation bar access r/w 1 = enable the shadowed downstream translation bar registers to be accessed. reset to 0. 6 upstream translation bar access r/w 1 = enable the shadowed upstream translation bar registers to be accessed. reset to 0. 7 ror write enable r/w read only registers write enable: subsystem vender id at register 2ch and subsystem id register at 2eh are normally read only. setting this bit to 1 will enable write to such read only id registers. power management regist ers deh, e0h, and e 3h are normally read only. setting this bit to 1 will enabl e write to all read only power management registers. this bit must be cleared after the desired values have been modified in the read only registers. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 66 6.3.4 gpio registers gpio[7:4] output data register - offset 9dh bit function type description 3:0 gpio[7:4] output write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit low on the gpio[7:4] bus if it is programmed as output. writing 0 has no effect. defaults to 0 7:4 gpio[7:4] output write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit high on the gpio[7:4] bus if it is programmed as output. writing 0 has no effect gpio[7:4] output enable register - offset 9eh bit function type description 3:0 gpio[7:4] output enable write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[7:4] bus as input only. writing 0 has no effect, reads returns last value written. defaults to 0 7:4 gpio[7:4] output enable write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[7:4] bus as output. gpio[7:4] then drives the value set in the output data register (reg 65h). writing 0 has no effect, reads returns last value written. defaults to 0 gpio[7:4] input data register - offset 9fh bit function type description 3:0 reserved r/o reserved 7:4 gpio[7:4] input data r/o this read-only register reads t he state of the gpio[7:4] pins. the state is updated on the pci clock cycle following a change in the gpio[7:4] state. power up status register - offset a0h bit function type description 7-0 power up status r/o power up latched status bits: upon pwrgd (power good), the status of gpio[15:8] are latched in this registers. user can choose to use such status for any desired option setting or checking. some recommended use (must be 3.3v input): gpio15: primary power state: 1 = primary port power is stable. gpio14: secondary power state: 1 = secondary port power is stable. gpio [15:8] output data register - offset a1h pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 67 bit function type description 7:0 gpio[15:8] output data r/w gpio[15:8] output data. defaults to 0 gpio [15:8] output enable register - offset a2h bit function type description 7:0 gpio[15:8] output enable r/w writing 1 to any of these bits drives the corresponding bit on the gpio[15:8] bus as output. defaults to 0 gpio[15:8] input data register - offset a3h bit function type description 7:0 gpio[15:8] input data r/o this read-only register reads t he state of the gpio[15:8] pins. the state is updated on the pci clock cycle following a change in the gpio[15:8] state. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 68 6.3.5 extended registers currently there are 8 32bit sticky sc ratch registers available in pci 6254 and they are at extended address 0h-7h. extended register index - offset d3h bit function type description 7:0 extended index address r/w index address for extended registers extended register dataport - offset d4h bit function type description 31:0 extended registers dataport r/w a configuration write will cause the data presented at this port to be written into the register addressed by the extended register index. a configuration read will cause the data from the register addressed by the extended register index to be presented to this port. extended registers register index 32 bit sticky register 0 0h 32 bit sticky register 1 1h 32 bit sticky register 2 2h 32 bit sticky register 3 3h 32 bit sticky register 4 4h 32 bit sticky register 5 5h 32 bit sticky register 6 6h 32 bit sticky register 7 7h 32 bit sticky scratch registers - extended register index 0h-7h bit function type description 31:0 scratch register r/w sticky scratch register. up on power good, their values are undefined. if power is good, p_rstin# and s_rstin# active inputs do not affect their pre-existing value. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 69 6.3.6 power management and hot swap registers power management registers deh, e0h, and e3h ar e normally read only. however their default value can be changed by firmware or software by setting the read only registers write enable bit at register. after any modifications to such registers, this write enable bit must be cleared to preserve their read only nature. capability identifier (r/o) ? offset dch this register is set to 01h to indicate power management interface registers. next item pointer (r/o) ? offset ddh set to e4h. this field provides an offset into the func tion's pci configuration space pointing to the location of next item in the function's capability list. in pc i 6254, this points to the hot swap registers. power management capabilities(r/o) ? offset deh this register is eeprom or ror write controlled loadable, but is read only during normal operation. bit function type description 0-2 version r/o this register is set to 001b, indicating that this function complies with rev 1.0 of the pci power management interface specification 3 pme clock r/o this bit is a '0', indicating that pci 6254 does not support pme# signaling. 4 auxiliary power source r/o this bit is set to ?0? since pci 6254 does not support pme# signaling 5 dsi r/o device specific initialization. returns ?0? indicating that pci 6254 does not need special initialization 6-8 reserved r/o reserved 9 d1 support r/o returns ?1? indicating that pci 6254 supports the d1 device power state 10 d2 support r/o returns ?1? indicating that pci 6254 supports the d2 device power state 11-15 pme support r/o set to ?0601? in revi sion aa. set to ?7e01? in revision ab. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 70 power management control/ status(r/w) ? offset e0h this register is eeprom or ror write controlled loadable, but is read only during normal operation. bit function type description 0-1 power state r/w this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. the definition of the field values is given below. 00b - d0 01b - d1 10b - d2 11b ? d3hot 2-7 reserved r/o reserved 8 pme enable r/w this bit is set to ?0? since pci 6254 does not support pme# signaling 9-12 data select r/o this field returns ?0000b? indicating pci 6254 does not return any dynamic data 13-14 data scale r/o returns ?00b? when read. pci 6254 does not return any dynamic data. 15 pme status r/w this bit is set to ?0? since pci 6254 does not support pme# signaling pmcsr bridge support(r/w) ? offset e2h bit function type description 0-5 reserved r/o reserved 6 b2/b3 support for d3hot r/o this bit reflects the state of t he bpcc input pin. a ?1? indicates that when pci 6254 is programmed to d3hot state the secondary bus?s clock is stopped. 7 bus power control enable r/o this bit reflects the state of the bpcc input pin. a ?1? indicates that the power management state of the seconda ry bus follows that of pci 6254 with one exception, d3hot state. power management data register (ro) ? offset e3h this register is eeprom or ror write controlled loadable, but is read only during normal operation. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 71 function capability identifier (r/o) ? offset e4h this register is set to 06h to indicate hot swap interface registers. next item pointer (r/o) - offset e5h set to e8h. this field provides an offset in to the function's pci configuration space pointing to the location of next item in the function's capabilit y list. in pci 6254, this points to the vital product data (vpd) registers. hot swap register(r/w) ? offset e6h bit type description 0 dha r/w device hiding arm. reset to 0. 1 = arm device hiding 0 = disarm device hiding dha is set to 1 by hardware during hot swap port pci rstin# going inactive and handle switch is still unlocked. the locking of the handle will clear this bit. 1 eim enum# mask status r/w enables or disables enum# assertion. reset to 0. 0 = enable enum# signal 1 = mask off enum# signal 2 pie r/o pending insert or extract: this bit is set when either ins or ext is ?1? or ins is armed (write 1 to ext bit). 1 = either an insertion or an extraction is in progress. 0 = neither is pending 3 1 = led is on loo led status r/w indicates if led is on or off. reset to 0. 0 = led is off 5-4 pi r/w programming interface: hardcode at 01: ins, est, loo, eim and pie, device hiding are supported. 6 ext extraction state r/w1c this bit is set by hardware when the ejector handle is unlocked and ins = 0. 7 ins insertion state r/w1c this bit is set by hardwar e when hot swap port rstin# is deasserted, eeprom autoload is comp leted and the ejector handle is locked. writing 1 to ext bit also arms ins. 15:8 reserved r/o reserved and a read returns all 0. write has no effect. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 72 this register is set to 03h to indicate vpd registers. bit 6.3.7 vpd registers capability identifier (r/o) - offset e8h next item pointer (r/o) - offset e9h set to 00h. vpd register (r/w) ? offset eah function type description 1-0 reserved r/o reserved 7-2 vpd address r/w writing a ?1? to this bit generates a write cycle to the eeprom at the vpd address specified in bits 7-2 of th is register. this bit will remain at a logic ?1? value until eeprom cycle is finished, then it be cleared to ?0?. vpd operation : writing a ?0? to this bit generates a read cycle from the eeprom at the vpd address specified in bits 7-2 of this register. this bit will remain at a logic ?0? value until eeprom cycle is finished, then it be set to ?1?. data for reads is available at register ech 14-8 reserved r/o reserved 15 vpd operation r/w vpd operation : writing a ?0? to this bit generates a read cycle from the eeprom at the vpd address specified in bits 7-2 of this register. this bit will remain at a logic ?0? value until eeprom cycle is finished, then it be set to ?1?. data for reads is available at register ech writing a ?1? to this bit generates a write cycle to the eeprom at the vpd address specified in bits 7-2 of th is register. this bit will remain at a logic ?1? value until eeprom cycle is finished, then it be cleared to ?0?. vpd data register (r/w) ? offset ech bit function type description 31-0 vpd data r/w vpd data (eeprom data[addr + 0x40]) - the least significant byte of this register corresponds to the byte of vpd at the address specified by the vpd address register. the data read from or written to this register uses the normal pci byte transfer capabilities. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 73 7 pci bus operation this chapter presents detailed information about pci tran sactions pci 6254 responds to and pci transactions initiated by pci 6254. 7.1 pci transactions table 7?1 lists the command code and name of each pci transaction that pci 6254 initiates and responds to. the master and target columns indicate support for eac h transaction when pci 6254 initiates transactions as a master, on the primary bus and on the secondary bus, and when pci 6254 responds to transactions as a target, on the primary bus and on the secondary bus. table 7?1, pci transactions initiates as master responds as target type of transaction primary secondary primary secondary 0000 interrupt acknowledge n n n n 0001 special cycle y y n n 0010 i/o read y y y y 0011 i/o write y y y y 0100 reserved n n n n 0101 reserved n n n n 0110 memory read y y y y 0111 memory write y y y y 1000 reserved n n n n 1001 reserved n n n n 1010 configuration read n y y n 1011 configuration write type-1 y y type-1 1100 memory read multiple y y y y 1101 dual address cycle y y y y 1110 memory read line y y y y 1111 memory write and invalidate y y y y as indicated in table 7?1, the following pci commands are not supported by pci 6254: x pci 6254 ignores reserved command codes and does not generate any reserved commands. x pci 6254 never initiates an interrupt acknowledge transact ion and, as a target, ignores interrupt acknowledge transactions. interrupt acknowledge transac tions are expected to reside entirely on the primary pci bus closest to the host bridge. x pci 6254 does not respond to special cycle transactions . to generate special cycle transactions on other pci buses, either upstream or downstream, a ty pe-1 configuration command must be used. x pci 6254 does not generate type-0 c onfiguration transactions on the primary interface. it will respond to type-0 configuration transactions on the secondary pci interface only if non-transparent mode is enabled. 7.2 single address phase a 32-bit address uses a single address phase. this address is driven on ad[31:0], and the bus command is driven on p_cbe[3:0] pci 6254 supports the linear increment address mode only, which is indicated when the low 2 address bits are equal to 0. if either of the low 2 address bits is nonzero , pci 6254 automatically disconnects the transaction after the first data transfer. 7.3 dual address phase pci 6254 supports the dual address cycle (dac) bu s command to transfer 64 -bit addresses. in dac transactions, the first address phase is during the initial assertion of frame, and the second address phase is one pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 74 x memory write type of transaction clock later. during the first address phase, the dac command is presented on cbe[3:0], the lower 32 bits of the address on ad[31:0]. the second address phase has t he cycle command on cbe[3:0], and the upper 32 bits of the address on ad[31:0]. when a 64-bit master uses dac, it must provi de the upper 32 bits of the address on ad[63:32] to and the command on cbe[7:4] during both addr ess phases of the transaction to allow 64-bit targets additional time to decode the transaction. dacs are used to access locations that are not in the first 4gb of pci memory space. addresses in the first 4gb of memory space always use a single address cycle (sac). pci 6254 supports dac in the upstream and downstream direction. pci 6254 responds to dac for the following commands only: x memory write and invalidate x memory read x memory read line x memory read multiple 7.4 device select (devsel#) generation pci 6254 always performs positive address decoding wh en accepting transactions on either the primary or secondary buses. pci 6254 never subtractively decodes . medium devsel# timing is used for 33mhz operation and slow devsel# timing is used for 66mhz operation. 7.5 data phase depending on the command type, pci 6254 can support mult iple data phase pci transactions. write transactions are treated as either posted wr ite or delayed write transactions. table 7?2 shows the method of forwarding used for each type of write operation. table 7?2, write transaction forwarding type of forwarding memory write posted memory write and invalidate posted i/o write delayed type-1 configuration write delayed 7.5.1 posted write transactions when pci 6254 determines that a memory write transaction is to be forwarded across the bridge, pci 6254 asserts devsel# with slow ti ming and trdy# in the same cycle, provided that enough buffer space is available in the posted write data queue, and there are less than 4 outstanding posted transactions in the queue. pci 6254 can accept 1 quad/dword of write data every pci clock cycle; that is, no target wait states are inserted. up to 256 bytes of posted write data is stored in internal post ed write buffers and is eventually delivered to the target. pci 6254 continues to accept write data until one of the following events occurs: x the initiator terminates the transaction normally. x a cache line boundary or an aligned 4kb boundary is reached, depending on the transaction type. x the posted write data buffer fills when one of the last two events occurs, pci 6254 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. once the posted write transaction is selected for completi on, pci 6254 requests ownership of the target bus. this can occur while pci 6254 is still receiving data on the init iator bus. once pci 6254 has ownership of the target bus, and the target bus is detected in the idle condition, pci 6254 generates the write cycle and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. as long as write data exists in the queue, pci 6254 can drive 1 quad/dword of write data each pci clock cycle. if write data is flowing through pci 6254 and t he initiator stalls, pci 6254 will insert wait states on the target bus if the queue empties. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 75 x the target returns a target abort (pci 6254 discards remaining write data). when the memory write and invalidate transaction is disconnected before a cache line boundary is reached, typically because the posted write data buffer fills, the tr ansaction is converted to a memory write transaction. pci 6254 ends the transaction on the target bus when one of the following conditions is met: x all posted write data has been delivered to the target. x the target returns a target disconnect or target retry (p ci 6254 starts another transaction to deliver the rest of the write data). the master latency timer expires, and pci 6254 no lo nger has the target bus grant (pci 6254 starts another transaction to deliver the remaining write data). 7.5.2 memory write and invalidate transactions memory write and invalidate transactions guarantee trans fer of entire cache lines. by default, pci 6254 will retry a memory write and invalidate cycle until there is space for at least 1 cache lin e of data in the internal buffers. it will then complete the transaction on the secondary bus as a memory write and invalidate cycle. pci 6254 can also be programmed to accept memory write and invalidat e cycles under the same conditions as normal memory writes. in this case, if the write buffer fills before an entire cache line is transferred, pci 6254 will disconnect and complete the write cycle on the secondary bus as a nor mal memory write cycle. (register 46, bit12). pci 6254 disconnects memory write and invalidate commands at aligned cache line boundaries. the cache line size value in the cache line size register gives the number of dw ords in a cache line. for pci 6254, to generate memory write and invalidate transactions, this cache line size value must be written to a value that is 8h, 10h, or 20h. if an invalid cache line size is programmed, wherein the value is 0, or is not a power of 2, or is greater than 20h dwords, pci 6254 sets the cache line size to the mini mum value of 8h. pci 6254 always disconnects on the cache line boundary. 7.5.3 delayed write transactions a delayed write transaction is used to forward i/o writ e and type-1 configuration cycles through pci 6254, and is limited to a single quad/dword data transfer. when a write transaction is first detected on the initia tor bus, pci 6254 claims the access and returns a target retry to the initiator. during the cycle, pci 6254 sample s the bus command, address, and address parity bits. pci 6254 also samples the first data quad/dword, byte enabl e bits, and data parity. cycle information is placed into the delayed transaction queue if there are no ot her existing delayed transactions with the same cycle information, and if the delayed transaction queue is not full. when pci 6254 schedules delayed write transaction to be the next cycle to be completed based on its ordering constraints, pci 6254 initiates the transaction on the target bus. pci 6254 transfers the write data to the target. if pci 6254 receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. if pci 6254 is unable to deliver write data after 2 24 attempts (programmable through register 45, bits 3-0), pci 6254 ceases further write attempts and returns a target abort to the initiator. the delayed transaction is removed from the delayed transaction queue. pci 6254 also asserts p_serr# if the primary serr# enable bit is set in the command register. when the initiator repeats the same write transaction (same command, address, byte enable bits, and data), after pci 6254 has completed data delivery, and has all the complete cycle information in the queue, pci 6254 claims the access returns trdy# to the init iator, to indicate that the write data was transferred. if the initiator requests multiple quad/dword, pci 6254 as serts stop# in conjunction with trdy# to signal a target disconnect. note that only those bytes of write data with valid byte enable bits are compared. if any of the byte enable bits are turned off (driven high), the corresponding byte of write data is not compared. if the initiator repeats the write tran saction before the data has been transf erred to the target, pci 6254 returns a target retry to the initiator. pci 6254 continues to return a target retry to t he initiator until write data is delivered to the target or an error condition is encountered. when t he write transaction is repeated, pci 6254 does not make a new entry into the delayed transaction queue. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 76 7.5.4 write transactio n address boundaries pci 6254 implements a discard timer that starts counting w hen the delayed write completion is at the head of the delayed transaction queue. the initial value of this timer can be set to one of four values, selectable through both the primary and the secondary master timeout bits in the bridge control register as well as the master timeout divider bits in register 45h. if the discard timer expire s before the write cycle is retried, pci 6254 discards the delayed write transaction from the delayed transaction queue. pci 6254 also conditionally asserts p_serr#. pci 6254 imposes internal address boundaries when acc epting write data. the aligned address boundaries are used to prevent pci 6254 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. pci 6254 returns a target disconnects to the initiator when it reaches the aligned address boundaries under the conditions shown in table 7?3. table 7?3, write transaction disconnect address boundaries type of transaction condition aligned address boundary delayed write all disconnects after one data transfer posted memory write memory write disconnect control bit = 0 1 4kb aligned address boundary posted memory write memory write disconnect control bit = 1 1 disconnects at cache line boundary posted memory write and invalidate cache line size = 8, 8h-dword aligned address boundary posted memory write and invalidate cache line size = 10h 10h-dword aligned address boundary posted memory write and invalidate cache line size = 20h 20h-dword aligned address boundary 1 - memory write disconnect control bit is located in the ch ip control register at offs et 40h in configuration space. 7.5.5 buffering multiple write transactions delayed write transactions are posted as long as at leas t one open entry in the delayed transaction queue exists. pci 6254 can queue up to four posted write transactions and four delayed transactions in both upstream and downstream directions. pci 6254 continues to accept posted memory write transacti ons as long as space for at least 1 dword of data in the posted write data buffer remains and there are less than 4 outstanding posted memory write cycles. if the posted write data buffer fills before the initiator terminates the write transaction, pci 6254 returns a target disconnect to the initiator. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 77 7.5.6 read transactions delayed read forwarding is used for all read transactions crossing pci 6254. delayed read transactions are treated as either prefetchable or nonprefetchable. table 7?4 shows the read behavior, prefetchable or nonprefetchable, for each type of read operation. table 7?4: read transaction prefetching type of transaction read behavior i/o read prefetching never done configuration read prefetching never done memory read downstream: prefetching us ed if address in prefetchable space upstream: prefetching used if pr efetch disable is off (default) memory read line prefetching always used if request is for more than one data transfer. memory read multiple prefetching always used if request is for more than one data transfer. 7.5.7 prefetchable read transactions a prefetchable read transaction is a read transacti on where pci 6254 performs speculative dword reads, transferring data from the target before it is requested from the initiator. th is behavior allows a prefetchable read transaction to consist of multiple data transfers. only the first byte enable bits can be forwarded. pci 6254 forces all byte enable bits of subsequent transfers to be enabled. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. the amount of the prefetched data depends on the type of transaction. the amount of prefetching may also be affected by the amount of free buffer space avail able in pci 6254, and by any read address boundaries encountered. in addition, there are several pci 6254-specifi c registers that can be used to optimize read prefetch behavior. prefetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, fifos, and so on. the target device?s base ad dress register or regi sters indicate if a memory address regi on is prefetchable. 7.5.8 nonprefetchable read transactions a nonprefetchable read transaction is r ead transaction by the initiator into a nonprefetchable region, and is used for i/o and configuration read transactions, as well as for memory read s from nonprefetchable memory space. in this case, pci 6254 requests 1 and only 1 dword from the target and disconnects the initiator after delivery of the first dword of read data. nonprefetchable read transactions should not be used for regions where extra read tran sactions could have side effects, such as fifo memory, or control registers. accordi ngly, if it is important to retain the value of the byte enable bits during the data phase, use nonprefetchable read transactions. if these locations are mapped in memory space, use the memory read command and map the target into nonprefetchable (memory-mapped i/o) memory space to utilize nonprefetching behavior. 7.5.9 read prefetch address boundaries pci 6254 imposes internal read address boundaries on read prefetching. the address boundary is used by pci 6254 to calculate the initial amount of data that it will pr efetch. during read transactions to prefetchable regions, pci 6254 will prefetch data until it reaches one of thes e aligned address boundaries, unless the target signals a target disconnect before the read prefetch boundary is reached. once the aligned address boundary is reached, pci 6254 may optionally continue prefetching data, dependi ng on certain conditions (see section on flow-through optimization). when pci 6254 finishes transferring this read dat a to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes t he transaction before all prefetched read data is delivered. any leftover prefetched data is discarded. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 78 prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4kb address boundary, or until the initiator deasserts frame#. table 7?5 shows the read prefetch address boundaries for read transactions during non-flow-through mode. table 7?5: read prefetch address boundaries type of transaction address space prefetch aligned address boundary configuration read - 1 dword (no prefetch) i/o read - 1 dword (no prefetch) memory read nonprefetchable 1 dword (no prefetch) memory read prefetchable configured through prefetch count registers memory read line prefetchable configur ed through prefetch count registers memory read multiple prefetchable config ured through prefetch count registers 7.5.10 delayed read requests pci 6254 treats all read transactions as delayed read trans actions, which means that the read request from the initiator is posted into a delayed transaction queue. read data from the target is placed in the read data queue directed toward the initiator bus interface and is transfer red to the initiator when t he initiator repeats the read transaction. when pci 6254 accepts a delayed read request, it firs t samples the read address, read bus command, and address parity. when irdy# is asserted, pci 6254 then sample s the byte enable bits for the first data phase. this information is entered into the delayed transaction qu eue. pci 6254 terminates the transaction by signaling a target retry to the initiator. upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response other than a target retry (target abort, or master abort) is received. 7.5.11 delayed read completion with target when a delayed read request is scheduled by pci 6254 to be executed, pci 6254 arbitrates for the target bus and initiates the read transaction, using the exact r ead address and read command captured from the initiator during the initial delayed read request. if the read transaction is a nonprefetchable read, pci 6254 drives the captured byte enable bits during the next cycle. if the transaction is a prefetchab le read transaction, it drives the captured first byte enable bits followed by 0 for the subse quent data phases. if pci 6254 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. if the transaction is terminated via normal master termination or target disconnect after at leas t one data transfer has been completed, pci 6254 does not initiate any further attempts to read more data. 7.5.12 delayed read completion on initiator bus if pci 6254 is unable to obtain read data from the target after 2 24 attempts (default), pci 6254 ceases further read attempts and returns a target abort to the initiato r. the delayed transaction is removed from the delayed transaction queue. pci 6254 also asserts p_serr# if the primary serr# enable bit is set in the command register. once pci 6254 receives devsel# and trdy # from the target, it transfers the data stored in the internal read fifo, before terminating the transaction. pci 6254 can accept 1 dword/qword of read data each pci clock cycle; no master wait states ar e inserted. the number of dword/qw ord transferred during a delayed read transaction depends on the conditions given in table 7?5 (assuming no disconnect is received from the target). when the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, pci 6254 transfers the data to the initiator when the initiator repeats the transaction. for memory read transactions, pci 6254 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 79 configuration transactions are used to initialize a pci sy stem. every pci device has a c onfiguration space that is accessed by configuration command s. all registers are accessible in configuration space only. in addition to accepting configuration transactions for initialization of its own c onfiguration space, pci 6254 forwards configuration transactions for device initialization in hierarchical pci systems, as well as for special cycle generation. type-0 configuration transactions are issued when the intended target resides on the same pci bus as the initiator. a type-0 configuration tran saction is identified by the configur ation command and the lowest 2 bits of the address set to 00b. of the transaction to the bus command in the delayed transaction queue. pci 6254 returns a target disconnect along with the transfer of the last dword of read data to the initiator. if pci 6254 initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. when the master repeats the transacti on and starts transferring prefetchabl e read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. in this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4kb address boundary is reached, or until the buffer fills, whichever comes first. when the buffer empties, pci 6254 reflects the stalled condition to the initiator by deasserting trdy# for a ma ximum of 8 clock periods until more r ead data is available; otherwise, pci 6254 will disconnect the cycle. when the initiator terminates the transaction, pci 6254 deassertion of frame# on the initiator bus is forwarded to the target bus. any remaining read data is discarded. pci 6254 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. the initial value of this timer is programmable through configuration r egister. if the initiator does not repeat the read transaction before discard timer expires, pci 6254 discards th e read transaction (and the read data from its queues). pci 6254 also conditionally asserts p_serr#. pci 6254 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. if an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not stored as it is already contained in the delayed transaction queue. 7.5.13 configuration transactions during non-transparent mode, pci 6254 c an also accept configuration transa ctions on its secondary interface (see non-transparent operation section). to support hierarchical pci bus systems, type-0 and type-1 configuration transa ctions are specified. type-1 configuration transactions ar e issued when the intended target resides on another pci bus, or when a special cycle is to be generated on another pci bus. a type-1 configuration command is identified by the configuration command and the lowest 2 address bits set to 01b. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 80 the register number is found in both type-0 and ty pe-1 formats and gives the dword address of the configuration register to be accessed. the function number is also included in both type-0 and type-1 formats and indicates which function of a multifunction device is to be accessed. for single-funct ion devices, this value is not decoded. type-1 configuration transa ction addresses also include a 5-bit field designating the device number that identifies the device on the target pci bus that is to be accessed. in addition, the bus number in type-1 transactions specifies the pci bus to which the transaction is targeted. 7.5.14 type-0 access to pci 6254 the configuration space is accessed by a type-0 conf iguration transaction on the primary interface. the configuration space cannot be accessed from the sec ondary bus. pci 6254 responds to a type-0 configuration transaction by asserting p_devse l# when the following conditions ar e met during the address phase: x the bus command is a configuration read transa ction or configuration write transaction. x low 2 address bits p_ad[1:0] must be 00b. x signal p_idsel must be asserted. pci 6254 limits all configuration accesses to a single dword data transfer and returns a target disconnect with the first data transfer if additional data phases are reque sted. because read transaction s to configuration space do not have side effects, all bytes in the requested dw ord are returned, regardless of the value of the byte enable bits. type-0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. pci 6254 ignores all type-0 transactions initiated on the secondary interface. 7.5.15 type-1 to type-0 translation type-1 configuration transactions are used specifically fo r device configuration in a hierarchical pci bus system. a pci-to-pci bridge is the only type of device that s hould respond to a type-1 configuration command. type-1 configuration commands are used when the configuration access is intended for a pci device that resides on a pci bus other than the one where the type-1 transaction is generated. pci 6254 performs a type-1 to type-0 translation when the type-1 transaction is generated on the primary bus and is intended for a device attached directly to the se condary bus. pci 6254 must convert the configuration command to a type-0 format so that the secondary bus dev ice can respond to it. type-1 to type-0 translations are performed only in the downstream direction; that is, pci 6254 generates a type-0 transaction only on the secondary bus, and never on the primary bus. pci 6254 responds to a type-1 configuration transaction and translates it into a type-0 transaction on the secondary bus when the following conditions are met during the address phase: x the low 2 address bits on p_ad[1:0] are 01b. x the bus number in address field p_ad[23:16] is equal to the value in the secondary bus number register in configuration space. x the bus command on p_cbe[3:0] is a configurati on read or configurati on write transaction. when pci 6254 translates the type-1 tr ansaction to a type-0 transaction on the secondary interface, it performs the following translations to the address: x sets the low 2 address bits on s_ad[1:0] to 00b. x decodes the device number and drives the bit pattern specified in table 7?6 on s_ad[31:16] for the purpose of asserting the device?s idsel signal. x sets s_ad[15:11] to 0. x leaves unchanged the function number and register number fields. pci 6254 asserts a unique address line based on the device number. these address lines may be used as secondary bus idsel signals. the mapping of the addr ess lines depends on the device number in the type-1 address bits p_ad[15:11]. table 7?6 pres ents the mapping that pci 6254 uses. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 81 table 7?6: device number to idsel s_ad pin mapping device number p_ad[15:11] secondary idsel s_ad[31:16] s_ad bit 0 00000 0000 0000 0000 0001 16 1 00001 0000 0000 0000 0010 17 2 00010 0000 0000 0000 0100 18 3 00011 0000 0000 0000 1000 19 4 00100 0000 0000 0001 0000 20 5 00101 0000 0000 0010 0000 21 6 00110 0000 0000 0100 0000 22 7 00111 0000 0000 1000 0000 23 8 01000 0000 0001 0000 0000 24 9 01001 0000 0010 0000 0000 25 10 01010 0000 0100 0000 0000 26 11 01011 0000 1000 0000 0000 27 12 01100 0001 0000 0000 0000 28 13 01101 0010 0000 0000 0000 29 14 01110 0100 0000 0000 0000 30 15 01111 1000 0000 0000 0000 31 special cycle 1xxxx 0000 0000 0000 0000 none pci 6254 can assert up to 16 unique address lines to be used as idsel signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 throu gh 15. because of electrical loading constraints of the pci bus, more than 16 idsel signals should not be neces sary. however, if device numbers greater than 15 are desired, some external method of generating idsel lines must be used, and no upper address bits are then asserted. the configuration tr ansaction is still translated and passed from the prim ary bus to the se condary bus. if no idsel pin is asserted to a secondary device, the transaction ends in a master abort. pci 6254 forwards type-1 to type-0 configuration read or write transactions as delayed transactions. type-1 to type-0 configuration read or write tran sactions are limited to a single 32-bi t data transfer. when type-1 to type-0 configurations cycles are forwarded, address stepping is used, valid address is driven on the bus before the frame# is asserted. type-0 configuration address steppi ng is programmable through register 46h, bits 6-4. 7.5.16 type-1 to type-1 forwarding type-1 to type-1 transaction forwarding provides a hier archical configuration mechanism when two or more levels of pci-to-pci bridges are used. when pci 6254 detects a type-1 configuration transaction intended for a pci bus downstream from the secondary bus, pci 6254 forwards the transaction unchanged to the secondary bus. ultima tely, this transaction is translated to a type-0 configuration command or to a s pecial cycle transaction by a downstream pci-to-pci bridge. downstream type-1 to type-1 forwarding occurs when the following conditions are met during the address phase: x the low 2 address bits are equal to 01b. x the bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. x the bus command is a configuratio n read or write transaction. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 82 pci 6254 also supports type-1 to type-1 forwarding of configuration write transacti ons upstream to support upstream special cycle generation. a type-1 configuration command is forwarded upstream when the following conditions are met: x x the low 2 address bits are equal to 01b. x the bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. x the device number in address bits ad[15:11] is equal to 11111b. x the function number in address bits ad[10:8] is equal to 111b. x the bus command is a configuration write transaction. pci 6254 forwards type-1 to type-1 configuration write transa ctions as delayed transactions. type-1 to type-1 configuration write transactions are limited to a single data transfer. 7.5.17 special cycles the type-1 configuration mechanism is used to generate sp ecial cycle transactions in hierarchical pci systems. special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. special cycle transactions can be generated fr om type-1 configuration write transacti ons in either the upstream or the downstream direction. pci 6254 initiates a special cycle on the target bus when a type-1 configuration write transaction is detected on the initiating bus and the following cond itions are met during the address phase: x the low 2 address bits on ad[1:0] are equal to 01b. x the device number in address bits ad[15:11] is equal to 11111b. x the function number in address bits ad[10:8] is equal to 111b. x the register number in address bits ad[7:2] is equal to 000000b. x the bus number is equal to the value in the secon dary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. x the bus command on cbe is a configuration write command. when pci 6254 initiates the transaction on the target inte rface, the bus command is changed from configuration write to special cycle. the address and data are forwarded unchanged. devices that use special cycles ignore the address and decode only the bus command. the data phase contains the sp ecial cycle message. the transaction is forwarded as a delayed transaction, but in this case t he target response is not forw arded back (because special cycles result in a master abort). once the transaction is completed on the target bus, through detection of the master abort condition, pci 6254 responds with trdy# to the next attempt of the configuration transaction from the initiator. if more than one data transfer is request ed, pci 6254 responds with a target disconnect operation during the first data phase. 7.6 transaction termination this section describes how pci 6254 returns transact ion termination conditions back to the initiator. the initiator can terminate transactions with one of the following types of termination: normal termination : it occurs when the initiator deasserts frame# at the beginning of the last data phase, and deasserts irdy# at the end of the last data phase in conjunction with either trdy# or stop# assertion from the target. x master abort : it occurs when no target response is detected. when the initiator does not detect a devsel# from the target within five clock cycles after assertin g frame#, the initiator terminates the transaction with a master abort. if frame# is still asserted, the initiator deasserts frame# on the next cycle, and then deasserts irdy# on the following cy cle. irdy# must be asserted in the same cycle in which frame# deasserts. if frame# is already deasserted, irdy# can be deasserted on the next clock cycle following detection of the master abort condition. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 83 x the target can terminate transactions with one of the following types of termination: normal termination: trdy# and devsel# asserted in conjunction with frame# deasserted and irdy# asserted. x target retry : stop# and devsel# asserted without trdy# duri ng the first data phase. no data transfers occur during the transaction. this transaction must be repeated. x target disconnect (with data transfer): stop# and devsel# asserted with t rdy#. signals that this is the last data transfer of the transaction. x target disconnect (w ithout data transfer) : stop# and devsel# asserted with out trdy# after previous data transfers have been made. indicates that no more data transfers will be made during this transaction. x target abort: stop# asserted without devsel# an d without trdy#. indicates t hat the target will never be able to complete this transaction. devsel# must be asserted for at least one cycle during the transaction before the target abort is signaled. 7.6.1 master termination initiated by pci 6254 pci 6254, as an initiator, uses normal termination if devsel# is re turned by the target within five clock cycles of pci 6254?s assertion of frame# on the target bus. as an initiator, pci 6254 terminates a transaction when the following conditions are met: x during a delayed write transaction, a single dword/qword is delivered. x during a nonprefetchable read transaction, a single dword/qword is transferred from the target. x during a prefetchable read transaction, a prefetch boundary is reached. x for a posted write transaction, all write data for the tr ansaction is transferred from data buffers to the target. x for a burst transfer, with the exception of memory writ e and invalidate transactions, the master latency timer expires and pci 6254?s bus grant is deasserted. x the target terminates the transaction wi th a retry, disconnect, or target abort. if pci 6254 is delivering posted write data when it terminat es the transaction because the master latency timer expires, it initiates another transaction to deliver t he remaining write data. the address of the transaction is updated to reflect the address of t he current dword to be delivered. if pci 6254 is prefetching read data when it terminates th e transaction because the master latency timer expires, it does not repeat the transaction to obtain more data. 7.6.2 master abort received by pci 6254 if the initiator initiates a transacti on on the target bus and does not detect d evsel# returned by the target within five clock cycles of pci 6254?s assertion of frame#, pci 6254 terminates the transaction as specified through the master abort mode bit of the bridge control register. for delayed read and write transactions, pci 6254 can eit her assert trdy# and return ffff_ffffh for reads, or return target abort. serr# is also optionally asserted. when a master abort is received in response to a posted write transaction, pci 6254 discards the posted write data and makes no more attempts to deliver the data. pci 6254 sets the received master abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is re ceived on the secondary interface. when a master abort is detected in response to a posted write transaction, and the master abort mode bit is set, pci 6254 also asserts p_serr# if enabled by the serr# enable bit in the command register and if not disabl ed by the device-specific p_serr# disable bit for master abort during posted writ e transactions (that is, master abort mode = 1; serr# enable bit = 1; and p_serr# disable bit for master aborts = 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 84 x pci 6254 completes at least one data transfer. x response 7.6.3 target termination received by pci 6254 when pci 6254 initiates a transaction on the target bus and the target responds with devsel#, the target can end the transaction with one of the following types of termination: x normal termination (upon deassertion of frame#) x target retry x target disconnect x target abort pci 6254 handles these terminations in different ways, depending on the type of transaction being performed. 7.6.3.1 delayed write target termination response when pci 6254 initiates a delayed write transaction, the type of target termination receiv ed from the target can be passed back to the initiator. table 7?7 shows the response to each type of target termination that occurs during a delayed write transaction. pci 6254 repeats a delayed write transaction unt il one of the following conditions is met: x pci 6254 receives a master abort. pci 6254 receives a target abort. pci 6254 makes 2 24 (default) write attempts resulting in a response of target retry. table 7?7: response to delaye d write target termination target termination normal return disconnect to initiato r with first data transfer only if multiple data phases requested. target retry return target retry to init iator. continue write attempts to target. target disconnect return disconnect to init iator with first data transfer only if multiple data phases requested. target abort return target abort to initiator. set received target abort bit in target interface status register. set signaled target abort bit in initiator interface status register. response after pci 6254 makes 2 24 attempts of the same delayed write transacti on on the target bus, pci 6254 asserts p_serr# if the primary serr# enable bit is set in the command register and t he implementation-specific p_serr# disable bit for this condition is not set in th e p_serr# event disable register. pci 6254 stops initiating transactions in response to that delayed write transac tion. the delayed write request is discarded. upon a subsequent write transaction attempt by the initiator, pci 6254 returns a target abort. 7.6.3.2 posted write targ et termination response when pci 6254 initiates a posted write transaction, the targ et termination cannot be passed back to the initiator. table 7?8 shows the response to each ty pe of target termination that occurs during a posted write transaction. table 7?8: response to posted write target termination target termination normal no additional action. target retry repeat writ e transaction to target. target disconnect initiate write transacti on to deliver remaining posted write data. target abort set received target abort bit in the target interface status register. assert p_serr# if enabled, and set the signaled system error bit in primary status register. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 85 after pci 6254 makes 2 nsaction attempts and fails to deliv er all the posted write data associated with that transaction, pci 6254 asserts p_serr# if the primar y serr# enable bit is set in the command register and the device-specific p_serr# disable bit for this condition is not set in the p_serr# event disable register. the write data is discarded. table 7?9: response to delayed read target termination note that when a target retry or target disconnect is returned and posted writ e data associated with that transaction remains in the write buffers, pci 6254 initiates another write transaction to attempt to deliver the rest of the write data. in the case of a target retry, the exact same address will be driven as for the initial write transaction attempt. if a target disconnect is received, the address that is driven on a subsequent write transaction attempt is updated to reflect the addres s of the current dword. if the initial write transa ction is a memory write and invalidate transaction, and a partial delivery of write dat a to the target is performed before a target disconnect is received, pci 6254 uses the memory write command to deliver the rest of the write data because less than a cache line will be transferred in the subsequent write transaction attempt. 24 write tra 7.6.3.3 delayed read target termination response when pci 6254 initiates a delayed read transaction, t he abnormal target responses can be passed back to the initiator. other target responses depend on how much dat a the initiator requests. t able 7?9 shows the response to each type of target termination that occurs during a delayed read transaction. target termination response normal if prefetchable, target disconnect only if initiator requests more data than read from target. if nonprefetchable, ta rget disconnect on first data phase. target retry reinitiate re ad transaction to target target disconnect if initiator requests more data than read from target, return target disconnect to initiator target abort return target abort to initiator. set received target abort bit in the target interface status register. set signaled target abort bit in the initiator interface status register. pci 6254 repeats a delayed read transaction unt il one of the following conditions is met: x pci 6254 completes at least one data transfer. x pci 6254 receives a master abort. x pci 6254 receives a target abort. after pci 6254 makes 2 the same delayed read transact ion on the target bus, pci 6254 asserts p_serr# if the primary serr# enable bit is set in the command register and t he implementation-specific p_serr# disable bit for this condition is not set in th e p_serr# event disable register. pci 6254 stops initiating transactions in response to that delayed read transact ion. the delayed read request is discarded. upon a subsequent read transaction attempt by the initiator, pci 6254 returns a target abort. x pci 6254 makes 2 24 read attempts resulting in a response of target retry. 24 attempts of pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 86 x a delayed read request with the same address and bus command has already been queued. 7.6.4 target termination initiated by pci 6254 pci 6254 can return a target retry, target disconnect, or target-abort to an initiator for reasons other than detection of that condition at the target interface. 7.6.4.1 target retry pci 6254 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. pci 6254 returns a target retry to an initiator when any of the following conditions is met: for delayed write transactions: x the transaction is being entered into the delayed transaction queue. x the transaction has already been entered into the delayed transaction queue, but target response has not yet been received. x target response has been received but the posted memory write ordering rule prevents the cycle from being completed. x the delayed transaction queue is full, and the transaction cannot be queued. x a transaction with the same address and command has been queued. x a locked sequence is being propagated across pci 6254, and the write transaction is not a locked transaction. x the target bus is locked and the write transaction is a locked transaction. for delayed read transactions: x the transaction is being entered into the delayed transaction queue. x the read request has already been queued, but read data is not yet available. x data has been read from the target, but it is not yet at the head of the read data queue, or a posted write transaction precedes it. x the delayed transaction queue is full, and the transaction cannot be queued. x a locked sequence is being propagated across pci 6254, and the read transaction is not a locked transaction. x the target bus is locked and the write transaction is a locked transaction. for posted write transactions: x the posted write data buffer does not have enough space for the address and at least two qwords of write data. x a locked sequence is being propagated across pci 6254, and the write transaction is not a locked transaction. when a target retry is returned to the initiator of a dela yed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if this is a write transaction, within the time frame specified by the master timeout value; otherwise , the transaction is discarded from the buffers. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 87 x 7.6.4.2 target disconnected pci 6254 returns a target disconnect to an initiator when one of the following conditions is met: x pci 6254 hits an internal address boundary x pci 6254 cannot accept any more write data x pci 6254 has no more read data to deliver 7.6.4.3 target-abort pci 6254 returns a target-abort to an initiator when one of the following conditions is met: x pci 6254 is returning a target abort from the intended target. pci 6254 detects a master abort on the target, and the master abort mode bit is set. x pci 6254 is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 2 24 attempts. when pci 6254 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 88 8 address decoding pci 6254 uses three address ranges that control i/o and memory transaction forwar ding. these address ranges are defined by base and limit address registers in the conf iguration space. this chapter describes these address ranges, as well as isa-mode and vga-addressing support. 8.1 address ranges pci 6254 uses the following address ranges that determin e which i/o and memory transactions are forwarded from the primary pci bus to the secondary pci bus , and from the secondary bus to the primary bus: x one 32-bit i/o address range x one 32-bit memory-mapped i/o (nonprefetchable memory) range x one 32-bit prefetchable memory address range transactions falling within these ranges are forwarded downstream from the primary pci bus to the secondary pci bus. transactions falling outside these ranges are forwarded upstream from the secondary pci bus to the primary pci bus. 8.2 i/o address decoding pci 6254 uses the following mechanisms that are defined in the configuration space to specify the i/o address space for downstream and upstream forwarding: x i/o base and limit address registers x the isa enable bit x the vga mode bit x the vga snoop bit this section provides information on the i/o address registers and isa mode. to enable downstream forwarding of i/o transactions, the i/o enable bit must be set in the command register in configuration space. if the i/o enable bit is not set, all i/o transactions initiated on the primary bus are ignored. to enable upstream forwarding of i/o transactions, the master enable bit must be set in the command register. if the master enable bit is not set, pci 6254 ignores all i/o and memory transactions initiated on the secondary bus. setting the master enable bit also allows upstream forwarding of memory transactions. caution: if any configuration state affecting i/o transacti on forwarding is changed by a configuration write operation on the primary bus at the same time that i/o transactions are ongoing on the secondary bus, the pci 6254 response to the secondary bus i/o transactions is not predictable. configure the i/o base and limit address registers, isa enable bit, vga mode bit, and vga snoop bit before setting the i/o enable and master enable bits, and change them subsequently only when the pr imary and secondary pci buses are idle. 8.2.1 i/o base and li mit address registers pci 6254 implements one set of i/o base and limit address registers in configuratio n space that define an i/o address range downstream forwarding . pci 6254 supports 32-bit i/o addressing, which allows i/o addresses downstream of pci 6254 to be mapped anywhere in a 4gb i/o address space. i/o transactions with addresses that fall inside the ran ge defined by the i/o base and lim it registers are forwarded downstream from the primary pci bus to the secondary pci bus. i/o transactions with addresses that fall outside this range are forwarded upstream from t he secondary pci bus to the primary pci bus. the i/o range can be turned off by setting the i/o base addr ess to a value greater than that of the i/o limit address. when the i/o ra nge is turned off, all i/o transactions are forwarded upstream, and no i/o transactions are forwarded downstream. the i/o range has a minimum granularity of 4kb and is aligned on a 4kb boundary. the maximum i/o range is 4gb in size. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 89 the i/o base register consists of an 8-bit field at conf iguration address 1ch, and a 16-bit field at address 30h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o base address. the bottom 4 bits read only as 1h to indicate that pci 6254 supports 32-bit i/o addressing. bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4kb boundary. the 16 bits contained in the i/o base upper 16 bits register at configuration offset 30h define ad[31:16] of the i/o ba se address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o base address is initialized to 0000_0000h. the i/o limit register consists of an 8-bit field at configur ation offset 1dh and a 16-bit fi eld at offset 32h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o limit address. the bottom 4 bits read only as 1h to indicate that 32-bit i/o addressing is supported. bits [11:0] of the li mit address are assumed to be fffh, which naturally aligns the limit address to the top of a 4kb i/o address block. the 16 bits contained in the i/o limit upper 16 bits register at configuration offset 32h define ad[31:16] of the i/o limit address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o limit address is reset to 0000 0fffh. note write these registers with their appropriate values befor e setting either the i/o enable bit or the master enable bit in the command register in configuration space. 8.3 isa mode pci 6254 supports isa mode by providing an isa enable bit in the bridge control register in configuration space. isa mode modifies the response of pci 6254 inside the i/o address range in order to support mapping of i/o space in the presence of an isa bus in the system. th is bit only affects the response of pci 6254 when the transaction falls inside the address range defined by the i/o base and limit address registers, and only when this address also falls inside the first 64kb of i/o space (address bits [31:16] are 0000h). when the isa enable bit is set, pci 6254 does not forwar d downstream any i/o transactions addressing the top 768 bytes of each aligned 1kb block. only those transac tions addressing the bottom 256 bytes of an aligned 1kb block inside the base and limit i/o address range are forwar ded downstream. transactions above the 64kb i/o address boundary are forwarded as defi ned by the address range defined by the i/o base and limit registers. accordingly, if the isa enable bit is set, pci 6254 forwar ds upstream those i/o transactions addressing the top 768 bytes of each aligned 1kb block within the first 64 kb of i/o space. the master enable bit in the command configuration register must also be set to enable upstr eam forwarding. all other i/o transactions initiated on the secondary bus are forwarded upstream only if they fall outside the i/o address range. when the isa enable bit is set, devices downstream of pci 6254 can have i/o space mapped into the first 256 bytes of each 1kb chunk below the 64kb boundary, or anywhere in i/o space above the 64kb boundary. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 90 8.4 memory address decoding pci 6254 has three mechanisms for defining memory addres s ranges for forwarding of memory transactions: x memory-mapped i/o base and limit address registers x prefetchable memory base and limit address registers x vga mode this section describes the first two mechanisms. to enable downstream forwarding of memory transactio ns, the memory enable bit must be set in the command register in configuration space. to enable upstream forwarding of memory transactions, the master enable bit must be set in the command register. setting the master enable bit also allows upstream forwarding of i/o transactions. caution if any configuration state affecting me mory transaction forwarding is chan ged by a configuration write operation on the primary bus at the same time that memory trans actions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. configure the memory-mapped i/o base and limit address registers, prefetchable memory base and limit address registers, and vga mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle. 8.4.1 memory-mapped i/o base and limit address registers memory-mapped i/o is also referred to as nonprefet chable memory. the memory-mapped i/o base address and memory-mapped i/o limit address registers define an addr ess range that pci 6254 uses to determine when to forward memory commands. pci 6254 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped i/o address range. pci 6254 ignores memory transactions initiated on the secondary interface that fall in to this address range. any transactions that fall outside this address range are ignored on the primary interface a nd are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memo ry range or are not forwarded downstream by the vga mechanism). the memory-mapped i/o range supports 32-bit addressing only. the pci-to-pci bridge architecture specification does not provide for 64-bit addressing in the memory-mapped i/o space. the memory-mapped i/o address range has a granularity and alignment of 1mb. the maximum memory-mapped i/o address range is 4gb. the memory-mapped i/o address range is defined by a 16-bit memory-mapped i/o base address register at configuration offset 20h and by a 16-bit memory-mapped i/o limit address register at offset 22h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the low 4 bits are hardwired to 0. the low 20 bits of the memory-mapped i/o base address ar e assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the low 20 bits of the memory-mapped i/o limit address are assumed to be f ffffh, which results in an alignment to the top of a 1mb block. note write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in th e command register in configuration space. to turn off the memory-mapped i/o address range, write the memory-mapped i/o base address register with a value greater than that of the memory-mapped i/o limit address register. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 91 the prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at o ffset 26h. the top 12 bits of each of these registers correspond to bits [31:20] of the me mory address. the low 4 bits are hardwired to 1h, indicating 64-bit address support. the low 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1mb bounda ry. the low 20 bits of the prefetchable memory limit address are assumed to be f_ffffh, which results in an alignment to the top of a 1mb block. 8.4.2 prefetchable memory b ase and limit addr ess registers locations accessed in the prefetchabl e memory address range must have true memory-like behavior and must not exhibit side effects when read. this means that extra reads to a prefetchable memory location must have no side effects. pci 6254 prefetches for all types of memory read commands in this address space. pci 6254 prefetchable memory base address and prefetch able memory limit address registers define an address range that pci 6254 uses to determine when to forward memory commands. pci 6254 forwards a memory transaction from the primary to the se condary interface if the transaction address falls within the prefetchable memory address range. pci 6254 ignores memory transactio ns initiated on the secondary interface that fall into this address range. pci 6254 does not respond to any tr ansactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped i/o range or are not forwarded by the vga mechanism). pci 6254 prefetchable memory range supports 64-bit addres sing and provides additional registers to define the upper 32 bits of the memory address range, pci 6254 pref etchable memory base address upper 32 bits register, and the prefetchable memory limit addres s upper 32 bits register. for address comparison, a single address cycle (32-bit address) prefetchable memory transaction is tr eated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. this upper 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. the prefetchable memory base address upper 32 bits regi ster must be 0 in order to pass any single address cycle transactions downstream. the prefetchable memory address range has a granularity and alignment of 1mb. the maximum memory address range is 4gb when 32-bit addressing is used, and 2 64 bytes when 64-bit addressing is used. note write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. to turn off the prefetchable memory address range, writ e the prefetchable memory base address register with a value greater than that of t he prefetchable memory limit address register. the entire ba se value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. therefore, to disable the address range, the upper 32 bits registers can bo th be set to the same value, while the lower base register is set greater than the lower limit register; otherwise, the upper 32 -bit base must be greater than the upper 32-bit limit. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 92 the vga i/o addresses consist of the following i/o addresses: 8.5 vga support pci 6254 provides two modes for vga support: x vga mode, supporting vga-compatible addressing x vga snoop mode, supporting vga palette forwarding 8.5.1 vga mode when a vga-compatible device exists downstream from pci 6254, set the vga mode bit in the bridge control register in configuration space to enable vga mode. when pci 6254 is operating in vga mode, it forwards downstream those transactions addressing the vga frame buffer memory and vga i/o registers, regardless of the values of the base and limit address registers. pci 6254 ignores transactions initiated on the secondary interface addressing these locations. the vga frame buffer consists of the following memory address range: 000a_0000h ? 000b_ffffh read transactions to frame buffer memory are treate d as nonprefetchable. pci 6254 requests only a single data transfer from the target, and read byte enabl e bits are forwarded to the target bus. x 3b0h?3bbh x 3c0h?3dfh these i/o addresses are aliased every 1kb throughout the first 64kb of i/o space. this means that address bits [15:10] are not decoded and can be any value, while address bits [31:16] must be all 0s. vga bios addresses starting at c0000h are not decoded in vga mode. 8.5.2 vga snoop mode pci 6254 provides vga snoop mode, allowing for vga pale tte write transactions to be forwarded downstream. this mode is used when a graphics device downstream from pci 6254 needs to snoop or respond to vga palette write transactions. to enable the mode, set the vga sno op bit in the command register in configuration space. note that pci 6254 claims vga palette write transactions by asserting devsel# in vga snoop mode. when the vga snoop bit is set, pci 6254 forwards downstream transactions with the following i/o addresses: x 3c6h x 3c8h x 3c9h note that these addresses are also forwarded as part of the vga compatibility mode previously described. again, address bits [15:10] are not decoded, while address bits [31:16] must be equal to 0, which means that these addresses are aliased every 1kb throug hout the first 64kb of i/o space. note if both the vga mode bit and the vga snoop bit are set, pci 6254 b ehaves in the same way as if only the vga mode bit were set. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 93 8.7.2 configuration addr ess translation operation x x x x 8.6 private device support in transparent mode, pci 6254 can support pci devices that are not visible at all to primary port hosts or masters. by connecting xb_mem input pin to ?1?, pci 6254 enable t he use of private memory at power up. the private memory range need to be setup by driv er software. pci 6254 will not respond to any a ccess to this private memory range on either the primary or the secondary port. 8.7 address translation pci 6254 has an address translation mechanism. addres s translation is supported for both upstream and downstream pci cycles. when enabled, pci cycles accessi ng a specific address range on the initiator bus will pass through to the target bus as the same cycle, but with a different address, as specified by the address translation registers. 8.7.1 base address registers pci 6254 supports a maximum of three address ranges that can be translated. the resource configuration is done through three base address registers, bar 0, bar 1 and bar 2. each bar has a 32-bit translation register and an 8-bit configuration register associated with it. bar 0 can be configured as a 32-bit i/o or memory bar. bar1 and bar2 are 32-bit bars, but can optionally be c onfigured as a single 64-bit memory bar. each bar follows the standard base address regist er definition described in the pci specification. there are two sets of these registers, one for upstream transl ation and one for downstream translation. each base address register has a programmable translati on address register. pci 6254 uses these registers to translate each cycle accessing memory or i/o space specified in one of the base address registers, if translation is enabled. this section will provide more specific details on progr amming the address translation registers of the pci 6254. as an example, it will show the typical sequence that would be performed by the secondary host. the secondary host first determines whic h resources it will make accessible to the host on the primary side of the bridge. it can provide any of the following combinations: one 32-bit i/o translated address range and one 64-bit memory translated address range one 32-bit i/o translated address range and tw o 32-bit memory translated address range one 32-bit memory translated address range a nd one 64-bit memory translated address range three 32-bit memory translated address range to specify the resources for the primary host, the secon dary host can program the downstream bar translation mask registers. these registers are used by the primary interface to c onfigure its base address registers. the first field in the translation mask register is used to specify the amount of addre ss space the device requires. the value programmed in this field is interpreted as a bit position into the corresponding bar in the primary configuration space. when bios tries to determine amount of address space requested by the bar by writing the value 0f ffffh and reading back the regi ster, the read value will return zeroes in all bit positions above the value specified in the translation mask register. for example, to request 4kb of address space, the bar should return ffff_f000h. this would be specified in the translation ma sk register by programming a value of bh (1011b) in the ?msb position of address mask field?. downstream bar0 translation mask regi ster has a bar type bit, bit 6, whic h can be used to specify if bar0 will specify an i/o or a memory range. this bit becomes reflected in bit 0 of the base address register at offset 10h of the primary configuration space. in a ddition, bit 7 specifies if the address register points to prefetchable address space or not, and is reflected in bits 1 and 2 of the corresponding address register if specified as a memory range. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 94 downstream bar1 translation mask register can only configure a memory base addr ess register in primary configuration register 14h. it can be configured as prefet chable or non-prefetchable through bit 7. in addition to this, bit 6 allows configuration as a 32-bit register or a 64-bit register. if programmed as a 64-bit register, then there is no need to program bar2 translation mask register. downstream bar2 translation mask register can configur e the third base address register as a 32-bit base address register only, and can be selected as prefetchable or non pref etchable address range. after programming the mask registers, the secondary host programs the downstream bar0, 1, and 2 translation address registers. the addres s programmed here would be the starting ad dress of each of the shared address space on the secondary interface address map. at this point, the secondary host has completed its programming, and it will then allow the primary side to be configured. the primary side base address registers ca n be configured by bios, but will still need software to enable translation by programming the downstream translation enable register at primary configuration register. alternately, all these registers can be programmed in to the eeprom device, to be autoloaded durin g power-up. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 95 9 transaction ordering to maintain data coherency and consistency, pci 6254 comp lies with the ordering rules set forth in the pci local bus specification, revision 2.2. 9.1 transaction ordering this section describes the ordering rules that control tr ansaction forwarding across pci 6254. for a more detailed discussion of transaction ordering, see appendix e of the pci local bus specification, revision 2.2. 9.1.1 transactions governed by ordering rules ordering relationships are established for the following classes of transactions crossing pci 6254: x posted write transactions, comprised of memory wr ite and memory write and invalidate transactions posted write transactions complete at the source before they complete at the des tination; that is, data is written into intermediate data buffe rs before it reaches the target. x delayed write request transactions, comprised of i/o write and configuration write transactions delayed write requests are terminated by target retr y on the initiator bus and are queued in the delayed transaction queue. a delayed write transaction must comp lete on the target bus before it completes on the initiator bus. x delayed write completion transactions, also comprise d of i/o write and configur ation write transactions. delayed write completion transactions have been completed on the target bus, and the target response is queued in the buffers. a delayed write completion transact ion proceeds in the direction opposite that of the original delayed write request; that is, a delayed write co mpletion transaction proceeds from the target bus to the initiator bus. x delayed read request transactions, comprised of a ll memory read, i/o read, and configuration read transactions. delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. x delayed read completion transactions, comprised of all memory read, i/o read, and configuration read transactions. delayed read completion transactions have been completed on the target bus, and the read data has been queued in the read data buffers. a delayed read comple tion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target?s bus to the initiator?s bus. pci 6254 does not combine or merge write transactions: x pci 6254 does not combine separate write transactions in to a single write transaction?this optimization is best implemented in the originating master. x pci 6254 does not merge bytes on separate masked writ e transactions to the same dword address?this optimization is also best implemented in the originating master. x pci 6254 does not collapse sequential write transa ctions to the same address into a single write transaction?the pci local bus specification does not permit this combining of transactions. 9.1.2 general ordering guidelines independent transactions on the primary and secondary buses have a relationship only when those transactions cross pci 6254. the following general ordering guidelines govern transactions crossing pci 6254: x the ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. x requests terminated with target retry can be accept ed and completed in any order with respect to other transactions that have been terminated with target re try. if the order of completion of delayed requests is important, the initiator should not start a second delay ed transaction until the first one has been completed. if more than one delayed transaction is initiated, the init iator should repeat all the delayed transaction requests, using some fairness algorithm. repeating a delayed transaction cannot be contingent on completion of another delayed transaction; ot herwise, a deadlock can occur. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 96 table 9?1 shows the ordering relationships of all the transact ions and refers by number to the ordering rules that follow. x write transactions flowing in one direction have no or dering requirements with respect to write transactions flowing in the other direction. pci 6254 can accept poste d write transactions on both interfaces at the same time, as well as initiate post ed write transactions on both interfaces at the same time. x the acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, nonposted transaction as a master. th is is true of pci 6254 and must also be true of other bus agents; otherwise, a deadlock can occur. x pci 6254 accepts posted write transacti ons, regardless of the state of completion of any delayed transactions being forwarded across pci 6254. 9.1.3 ordering rules table 9?1: summary of transaction ordering pass posted write delayed read request delayed write request delayed read completion delayed write completion posted write n 1 y 5 y 5 y 5 y 5 delayed read request n 2 y y y y delayed write request n 4 y y y y delayed read completion n 3 y y y y delayed write completion y y y y y note the superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. many entries are not governed by these ordering rules; therefore, the implementation c an choose whether or not the transactions pass each other. the entries without superscripts reflect pci 6254?s implementation choices. the following ordering rules describe the transaction relationships. each ordering rule is followed by an explanation, and the ordering rules are referred to by num ber in table 9?1. these ordering rules apply to posted write transactions, delayed write and read requests, and delay ed write and read completion transactions crossing pci 6254 in the same direction. note that delayed co mpletion transactions cross pci 6254 in the direction opposite that of the corresponding delayed requests. 1. posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. the subsequent posted write transaction can be setting a fl ag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. 2. a delayed read request traveling in the same directi on as a previously queued posted write transaction must push the posted write data ahead of it. the posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. the read transaction can be to the same location as the wr ite data, so if the read transaction were to pass the write transaction, it would return stale data. 3. a delayed read completion must ??pull?? ahead of previo usly queued posted write data traveling in the same direction. in this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of the as the target of the write tr ansaction. the posted write transaction must complete to the target before the read data is returned to the initiator. the read transaction can be to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. delayed write requests cannot pass previously queued posted write data. as in the case of posted memory write transactions, the delayed write transaction can be se tting a flag that covers the data in the posted write transaction; if the delayed write request were to complete before the earlier posted wr ite transaction, a device checking the flag could subse quently consume stale data. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 97 5. posted write transactions must be given opport unities to pass delayed read and write requests and completions. otherwise, deadlocks may occur when bridge s that support delayed transactions are used in the same system with bridges that do not support delayed tr ansactions. a fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue. pci 6254 can generate cycles across the bridge in the same order than requested if bit 2 of register 46h is set. by default, requested cycles can execute out of order across the bridge, if a ll other ordering rules are satisfied. so, if pci 6254 starts a delayed transaction that is retri ed by the target, it can execute another transaction in the delayed transaction request queue. also, if there is both delayed read and delayed write requests in the queue, and the read data fifo?s are full, pci 6254 may execut e the delayed write request before the delayed read request. on cycle completion, pci 6254 may complete cycles in a different order than requested by the initiator. 9.1.4 data synchronization data synchronization refers to the relationship betwe en interrupt signaling and data delivery. the pci local bus specification, revision 2.2, provides the following alternative methods for sync hronizing data and interrupts: x the device signaling the interrupt performs a read of the data just written (software). x the device driver performs a read operation to any register in the interruptin g device before accessing data written by the device (software). x system hardware guarantees that write buffers are flushed before interrupts are forwarded. pci 6254 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the sa me path), or from the device driver to one of the device registers. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 98 pci 6254 checks, forwards, and generates parity on both the primary and secondary interfaces. to maintain transparency, pci 6254 always tries to forward the existi ng parity condition on one bus to the other bus, along with address and data. pci 6254 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. x pci 6254 sets the detected parity error bit in the status register. 10 error handling to support error reporting on the pci bus, pci 6254 implements the following: x perr# and serr# signals on both the primary and secondary interfaces x primary status and seconda ry status registers x the device-specific p_serr# event disable register x the device-specific p_serr# status register x for non-transparent mode, the device-specific s_serr# event disable register x for non-transparent mode, the device- specific s_serr# status register this chapter provides detailed information about how pci 6254 handles errors. it also describes error status reporting and error operation disabling. 10.1 address parity errors pci 6254 checks address parity for all transactions on both buses, for all address and all bus commands. when pci 6254 detects an address parity error on th e primary interface, the following events occur: x if the parity error response bit is set in the command register, pci 6254 does not claim the transaction with p_devsel#; this may allow the transact ion to terminate in a master-abort. if the parity error response bit is not set, pci 6254 proceeds normally and accepts the transa ction if it is directed to or across pci 6254. x pci 6254 asserts p_serr# and sets the signaled system error bit in the status register, if both of the following conditions are met: i the serr# enable bit is set in the command register. i the parity error response bit is set in the command register. when pci 6254 detects an address parity error on th e secondary interface, t he following events occur: x if the parity error response bit is se t in the bridge control register, pci 6254 does not claim the transaction with s_devsel#; this may allow the transaction to term inate in a master abort. if the parity error response bit is not set, pci 6254 proceeds normally and accepts the trans action if it is directed to or across pci 6254. x pci 6254 sets the detected parity error bi t in the secondary status register. x pci 6254 asserts p_serr# and sets the signaled system error bit in the status register, if both of the following conditions are met: i the serr# enable bit is set in the command register. i the parity error response bit is set in the bridge control register. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 99 x pci 6254 forwards the bad parity with the data back to the initiator on the primary bus. 10.2 data parity errors when forwarding transactions, pci 6254 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to a llow the master and target devices to handle the error condition. the following sections describe, for each type of transa ction, the sequence of events that occurs when a parity error is detected and the way in which the parit y condition is forwarded across the bridge. 10.2.1 configuration write transa ctions to configuration space when pci 6254 detects a data parity error during a type-0 c onfiguration write transaction to configuration space, the following events occur: x if the parity error response bit is set in the command register, pci 6254 asserts p_trdy# and writes the data to the configuration register. pci 6254 also asserts p_perr#. if the parity error response bit is not set, pci 6254 does not assert p_perr#. x pci 6254 sets the detected parity error bit in the status register, regardless of t he state of the parity error response bit. 10.2.2 read transactions when pci 6254 detects a parity error during a read trans action, the target drives data and data parity, and the initiator checks parity and conditionally asserts perr#. for downstream transactions, when pci 6254 detects a read data parity error on the secondary bus, the following events occur: x pci 6254 asserts s_perr# two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. x pci 6254 sets the detected parity error bi t in the secondary status register. x pci 6254 sets the data parity detected bi t in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. if the data with the bad parity is prefetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. x pci 6254 completes the transaction normally. for upstre am transactions, when pci 6254 detects a read data parity error on the primary bus, the following events occur: x pci 6254 asserts p_perr# two cycles following the dat a transfer, if the primary interface parity error response bit is set in the command register. x pci 6254 sets the detected parity error bi t in the primary status register. x pci 6254 sets the data parity detected bit in the primary status register, if the primary interface parity error response bit is set in the command register. x pci 6254 forwards the bad parity with the data ba ck to the initiator on the secondary bus. if the data with the bad parity is prefetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. x pci 6254 completes the transaction normally. pci 6254 returns to the initiator the data and parity that was received from the target. when the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts perr# two cycles after the data transfer occurs. it is assumed that the initiator takes responsibility for han dling a parity error co ndition; therefore, when pci 6254 detects perr# asserted while returning read data to the initiator, pci 6254 does not take any further action and completes the transaction normally. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 100 x 10.2.3 delayed write transactions when pci 6254 detects a data parity error during a delayed write transaction, the in itiator drives data and data parity, and the target checks parity and conditionally asserts perr#. for delayed write transactions, a parity error can occur at the following times: x during the original delayed write request transaction x when the initiator repeats the delayed write request transaction x when pci 6254 completes the delayed write transaction to the target when a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the in itiator. when pci 6254 detects a parity error on the write data for the initial delayed write request transaction, the following events occur: x if the parity error response bit corresponding to the initiator bus is set, pci 6254 asserts trdy# to the initiator and the transaction is not queued. if multiple data phases are requested, stop# is also asserted to cause a target disconnect. two cycles after the data transfer, pci 6254 also asserts perr#. if the parity error response bit is not set, pci 6254 return s a target retry and queues the transaction as usual. signal perr# is not asserted. in this ca se, the initiator repeats the transaction. pci 6254 sets the detected parity error bit in the status register corresponding to the initiator bus, regardless of the state of the parity error response bit. note if parity checking is turned off and data parity errors have o ccurred for queued or subsequent delayed write transactions on th e initiator bus, it is possible that the initiator?s reattempts of the write transaction may not ma tch the original queued delaye d write information contained in the delayed transaction queue. in this case, a master timeout condition may occur, possibly resulting in a system error (p_serr# assertion). for downstream transactions, when pci 6254 is delivering data to the target on the secondary bus and s_perr# is asserted by the target, the following events occur: x pci 6254 sets the secondary interface data parity det ected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. x pci 6254 captures the parity error condition to forw ard it back to the initiator on the primary bus. similarly, for upstream transactions, when the is delivering data to the target on the primary bus and p_perr# is asserted by the target, the following events occur: x pci 6254 sets the primary interface data parity detected bit in the status register, if the primary parity error response bit is set in the command register. x pci 6254 captures the parity error condition to forw ard it back to the initiator on the secondary bus. a delayed write transaction is completed on the initiator bu s when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. two cases must be considered: x when parity error is detected on the initiator bus on a subsequent reattempt of the transaction and was not detected on the target bus x when parity error is forwarded back from the target bus x for downstream delayed write transactions, when the pa rity error is detected on the initiator bus and pci 6254 has write status to return, the following events occur: x pci 6254 first asserts p_trdy# and then asserts p_perr# two cycles later, if the primary interface parity error response bit is set in the command register. x pci 6254 sets the primary interface parity e rror detected bit in the status register. x because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 101 x because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. x pci 6254 completes the transaction normally. i the device-specific p_serr# disable bit for posted write parity errors is not set. similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and pci 6254 has write status to return, the following events occur: x pci 6254 first asserts s_trdy# and then asserts s_perr# two cycles later, if the secondary interface parity error response bit is set in the bridge control register. x pci 6254 sets the secondary interface parity error detected bit in the secondary status register. for downstream transactions, in the case where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: x pci 6254 asserts p_perr# two cycles after the dat a transfer, if both of the following are true: i the primary interface parity error response bit is set in the command register. i the secondary interface parity error response bit is set in the bridge control register. x pci 6254 completes the transaction normally. for upstream transactions, in the case where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: x pci 6254 asserts s_perr# two cycles after the dat a transfer, if both of the following are true: i the primary interface parity error response bit is set in the command register. i the secondary interface parity error response bit is set in the bridge control register. x pci 6254 completes the transaction normally. 10.2.4 posted write transactions during downstream posted write transactions, when the pci 6254, responding as a target, detects a data parity error on the initiator (primary) bus, the following events occur: x pci 6254 asserts p_perr# two cycles after the data transfer, if the primary interface parity error response bit is set in the command register. x pci 6254 sets the primary interface parity e rror detected bit in the status register. x pci 6254 captures and forwards the bad parity condition to the secondary bus. x pci 6254 completes the transaction normally. similarly, during upstream posted write transactions, when the pci 6254, responding as a target, detects a data parity error on the initiator (seconda ry) bus, the following events occur: x pci 6254 asserts s_perr# two cycles after the data transf er, if the secondary interface parity error response bit is set in the bridge control register. x pci 6254 sets the secondary interface parity error detected bit in the secondary status register. x pci 6254 captures and forwards the bad parity condition to the primary bus. during downstream write transactions, when a data parity er ror is reported on the target (secondary) bus by the target?s assertion of s_perr#, the following events occur: x pci 6254 sets the data parity detected bi t in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. x pci 6254 asserts p_serr# and sets the signaled system error bit in the status register, if all of the following conditions are met: i the serr# enable bit is set in the command register. i the secondary interface parity error response bit is set in the bridge control register. i the primary interface parity error response bit is set in the command register. i pci 6254 did not detect the parity error on the primary (initiator) bus; that is, the parity error was not forwarded from the primary bus. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 102 bus where error was detected during upstream write transactions, when a data parity error is reported on the target (primary) bus by the target?s assertion of p_perr#, the following events occur: x pci 6254 sets the data parity detected bit in the status r egister, if the primary interface parity error response bit is set in the command register. x pci 6254 asserts p_serr# and sets the signaled system erro r bit in the status register, if all of the following conditions are met: i the serr# enable bit is set in the command register. i the secondary interface parity error response bit is set in the bridge control register. i the primary interface parity error response bit is set in the command register. i pci 6254 did not detect the parity error on the secondary (initiator) bus; that is , the parity error was not forwarded from the secondary bus. the assertion of p_serr# is used to signal the parity error condition in the case where the initiator does not know that the error occurred. becaus e the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. if the parity error was forwarded from the initiating bus to the target bus, p_ serr# is not asserted. 10.3 data parity error reporting summary in the previous sections, pci 6254?s responses to data parity errors are presented according to the type of transaction in progress. this section organizes pci 6254?s re sponses to data parity errors according to the status bits that pci 6254 sets and the signals that it asserts. table 10?1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. this bit is set when pci 6254 detects a parity error on the primary interface. table 10?1: setting the primary interface detected parity error bit primary detected parity error bit transaction type direction prim./sec. parity error response bits 0 primary read downstream x/x 1 0 read downstream secondary x/x 1 read upstream primary x/x 0 read upstream secondary x/x 1 posted write downstream primary x/x 0 posted write downstream secondary x/x 0 posted write upstream primary x/x 0 posted write upstream secondary x/x 1 delayed write downstream primary x/x 0 delayed write downstream secondary x/x 0 delayed write upstream primary x/x 0 delayed write upstream secondary x/x 1 x = don?t care pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 103 table 10?2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. this bit is set when pci 6254 detects a parity error on the secondary interface. table 10?2: setting the secondary interface detected parity error bit sec. detected parity error bit transaction type direction bus where error was detected prim./sec. parity error response bits 0 read downstream primary x/x 1 1 read downstream secondary x/x 0 read upstream primary x/x 0 read upstream secondary x/x 0 posted write downstream primary x/x 0 posted write downstream secondary x/x 0 posted write upstream primary x/x 1 posted write upstream secondary x/x 0 delayed write downstream primary x/x 0 delayed write downstream secondary x/x 0 delayed write upstream primary x/x 1 delayed write upstream secondary x/x 1 x = don?t care table 10?3 shows setting the data parity detected bit in the status register, co rresponding to the primary interface. this bit is set under the following conditions: x pci 6254 must be a master on the primary bus. x the parity error response bit in the command register , corresponding to the primary interface, must be set. x the p_perr# signal is detected asserted or a parity error is detected on the primary bus. table 10?3: setting the primary interface data parity detected bit primary data parity detected bit transaction type direction bus where error was detected prim./sec. parity error response bits 0 read downstream primary x/x 1 0 read downstream secondary x/x 1 read upstream primary 1/x 0 read upstream secondary x/x 0 posted write downstream primary x/x 0 posted write downstream secondary x/x 1 posted write upstream primary 1/x 0 posted write upstream secondary x/x 0 delayed write downstream primary x/x 0 delayed write downstream secondary x/x 1 delayed write upstream primary 1/x 0 delayed write upstream secondary x/x 1 x = don?t care table 10?4 shows setting the data parity detected bit in the secondary status register, corresponding to the secondary interface. this bit is set under the following conditions: x pci 6254 must be a master on the secondary bus. x the parity error response bit in the bridge control regi ster, corresponding to the secondary interface, must be set. x the s_perr# signal is detected asserted or a parity error is detected on the secondary bus. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 104 table 10?4: setting the secondary interface data parity detected bit secondary data parity detected bit transaction type direction bus where error was detected prim./sec. parity error response bits 0 read downstream primary x/x 1 1 read downstream secondary x/1 0 read upstream primary x/x 0 read x/x upstream secondary 0 posted write downstream primary x/x 1 posted write downstream secondary x/1 0 posted write upstream primary x/x 0 posted write upstream secondary x/x 0 delayed write downstream primary x/x 1 delayed write downstream secondary x/1 0 delayed write upstream primary x/x 0 delayed write upstream secondary x/x 1 x =don?t care table 10?5 shows assertion of p_perr#. this signal is set under the following conditions: x pci 6254 is either the target of a write transaction or the initiator of a read tran saction on the primary bus. x the parity error response bit in the command register , corresponding to the primary interface, must be set. x pci 6254 detects a data parity error on the primary bu s or detects s_perr# asserted during the completion phase of a downstream delayed write tran saction on the target (secondary) bus. table 10?5: assertion of p_perr# p_perr# transaction type direction bus where error was detected prim./sec. parity error response bits 1 (deasserted) read downstream primary x/x 1 1 read downstream secondary x/x 0 (asserted) read upstream primary 1/x 1 read upstream secondary x/x 0 posted write downstream primary 1/x 1 posted write downstream secondary x/x 1 posted write upstream primary x/x 1 posted write upstream secondary x/x 0 delayed write downstream primary 1/x 0 2 delayed write downstream secondary 1/1 1 delayed write upstream primary x/x 1 delayed write upstream secondary x/x 1 x = don?t care 2 th e parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. x pci 6254 detects a data parity error on the secondary bus or detects p_perr# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. table 10?6 shows assertion of s_perr#. this signal is set under the following conditions: x pci 6254 is either the target of a write transaction or the initiator of a read tran saction on the secondary bus. x the parity error response bit in the bridge control regi ster, corresponding to the secondary interface, must be set. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 105 bus where error was detected table 10-6: assertion of s_perr# s_perr# transaction type direction prim./sec. parity error response bits 1 (deasserted) read downstream primary x/x 1 0 (asserted) read downstream secondary x/1 1 read upstream primary x/x 1 read upstream secondary x/x 1 posted write downstream primary x/x 1 posted write downstream secondary x/x 1 posted write upstream primary x/x 0 posted write upstream secondary x/1 1 delayed write downstream primary x/x 1 delayed write downstream secondary x/x 0 2 delayed write upstream primary 1/1 0 delayed write upstream secondary x/1 1 x =don?t care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. table 10?7 shows assertion of p_serr#. this signal is set under the following conditions: x pci 6254 has detected p_perr# asserted on an upstream posted write transaction or s_perr# asserted on a downstream posted write transaction. x pci 6254 did not detect the parity error as a target of the posted write transaction. x the parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. x the serr# enable bit must be set in the command register. table 10?7: assertion of p_se rr# for data parity errors p_perr# transaction type direction bus where error was detected prim./sec. parity error response bits 1 (deasserted) read downstream primary x/x 1 1 read downstream secondary x/x 1 read upstream primary x/x 1 read upstream secondary x/x 1 posted write downstream primary x/x 0 2 (asserted) posted write downstream secondary 1/1 0 3 posted write upstream primary 1/1 1 posted write upstream secondary x/x 1 delayed write downstream primary x/x 1 delayed write downstream secondary x/x 1 delayed write upstream primary x/x 1 delayed write upstream secondary x/x 1 x = don?t care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 the parity error was detected on the target (primary) bus but not on the initiator (secondary) bus. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 106 x x x x delayed read data cannot be transferred from target after 2 ( 2 received) most of these events have additional device-specific disable bits in the p_serr# event disable register that make it possible to mask out p_serr# assertion for specific events. the master timeout condition has a serr# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit. 10.4 system error (serr#) reporting whenever the assertion of p_serr# is discussed in this document, it is assumed that the following conditions apply: x for pci 6254 to assert p_serr# for any reason, the se rr# enable bit must be se t in the command register. x whenever pci 6254 asserts p_serr#, pci 6254 must also set the signaled system er ror bit in the status register. in compliance with the pci-to-pci bridge architecture specification, pci 6254 asserts p_serr# when it detects the secondary serr# input, s_serr#, asserted and the serr# forward enable bit is set in the bridge control register. in addition, pci 6254 also sets the received system error bit in the secondary status register. pci 6254 also conditionally asserts p_serr# for any of the following reasons: x target abort detected during posted write transaction master abort detected during posted write transaction x posted write data discarded after 2 attempts to deliver (2 target retries received) 24 24 parity error reported on target bus during pos ted write transaction (see previous section) delayed write data discarded after 2 attempts to deliver (2 target retries received) 24 24 24 attempts 24 target retries x master timeout on delayed transaction the device-specific p_serr# stat us register reports the reason for the assertion of p_serr#. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 107 11 exclusive access this chapter describes the use of the lock# signal to im plement exclusive access to a target for transactions that cross pci 6254. current revision of the pci 6254 does not support locked burst read cycles . 11.1 concurrent locks the primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses pci 6254. a primary master can lock a primary target wit hout affecting the status of the lock on the secondary bus, and vice versa. this means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target. 11.2 acquiring exclusive access across pci 6254 for any pci bus, before acquiring access to the lock# sign al and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: x the pci bus must be idle. x the lock# signal must be deasserted. the initiator leaves the lock# signal deasserted during the address phase and asserts lock# one clock cycle later. once a data transfer is completed from the target, the target lock has been achieved. locked transactions can cross pci 6254 in the downstream and upstream directions, from the primary bus to the secondary bus and vice versa. when the target resides on another pci bus, the master must acquire not only the lock on its own pci bus but also the lock on every bus between its bus and the target ?s bus. when pci 6254 detects, on the primary bus, an initial locked transaction intended for a target on the secondary bus, pci 6254 samples the address, transaction type, byte enable bits, and parity. it also samples the lock si gnal. because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. the first locked transaction must be a read transacti on. subsequent locked transac tions can be read or write transactions. posted memory write tran sactions that are a part of the locked transaction sequence are still posted. memory read transactions that are a part of the locked transaction se quence are not prefetched. when the locked delayed read request is queued, pci 6254 does not queue any more transactions until the locked sequence is finished. pci 6254 signals a target retr y to all transactions initiated subsequent to the locked read transaction that are intended for targets on the ot her side of pci 6254. pci 6254 allows any transactions queued before the locked transaction to complete before initiating the locked transaction. when the locked delayed read request transaction moves to the head of t he delayed transaction queue, pci 6254 initiates the transaction as a locked read transaction by deasserting lock# on the target bus during the first address phase, and by asserting lock# one cycle later. if lock# is already asserted (used by another initiator), pci 6254 waits to request access to the secondary bus until lock# is sampled deasserted when the target bus is idle. note that the existing lock on the target bu s could not have crossed pci 6254; otherwise, the pending queued locked transaction would not have been queued. when pci 6254 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. when the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, pci 6254 transfers the read data back to the initiator, and the lock is then also established on the primary bus. for pci 6254 to recognize and respond to the initiator, the initiator?s subsequent attempts of the read transaction must use the locked transaction sequence (deassert lo ck# during address phase, an d assert lock# one cycle later). if the lock# sequence is not used in subsequent a ttempts, a master timeout condition may result. when a master timeout condition occurs, serr# is conditionally asserted, the read data and queued read transaction are discarded, and the lock# signal is deasserted on the target bus. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 108 when the last locked transaction is a delayed transacti on, pci 6254 has already completed the transaction on the secondary bus. in this case, as soon as pci 6254 detect s that the initiator has reli nquished the lock# signal by sampling it in the deasserted state while frame# is deasserted, pci 6254 deasserts the lock# signal on the target bus as soon as possible. because of this behavio r, lock# may not be deasserted until several cycles after the last locked transaction has been completed on the tar get bus. as soon as pci 6254 has deasserted lock# to indicate the end of a sequence of locked transac tions, it resumes forwarding unlocked transactions. once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by pci 6254 are driven as locked transactions on the target bus. when pci 6254 receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. pci 6254 resumes forwarding unlocked transactions in both directions. 11.3 ending exclusive access after the lock has been acquired on both the initiator and ta rget buses, pci 6254 must maintain the lock on the target bus for any subsequent locked transactio ns until the initiator relinquishes the lock. the only time a target retry causes the lock to be relinquish ed is on the first transaction of a locked sequence. on subsequent transactions in the sequence, the target re try has no effect on the status of the lock signal. an established target lock is maintained until the initia tor relinquishes the lock. pci 6254 does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator deasserts the lock# signal at the end of the transaction. when the last locked transaction is a posted write tran saction, pci 6254 deasserts lock# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. when pci 6254 receives a target abort or a master abort in response to a locked delayed transaction, pci 6254 returns a target abort or a master abort when the initiato r repeats the locked transacti on. the initiator must then deassert lock# at the end of the transaction. pci 6254 se ts the appropriate status bits, flagging the abnormal target termination condition. normal forwarding of unlocked posted and delayed transactions is resumed. when pci 6254 receives a target abort or a master abort in response to a locked posted write transaction, pci 6254 cannot pass back that status to the initiator. pci 6254 asserts serr# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the serr# enable bit is set in the command register. signal serr# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register. note: pci 6254 has an option to ignore the lock protocol , through register 46h, bits 13 and 14. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 109 pci 6254 has a 2-level arbitration scheme in which arbitration is divided into two groups, a high priority group and a low priority group. the low priority group as a whole repr esents one entry in the high prio rity group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. priority changes evenly among t he low priority group. theref ore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. each master can be assigned to either the low pr iority group or the high priority group, through configuration register 42h. 12 pci bus arbitration pci 6254 must arbitrate for use of the primary bus when forwarding upstream transac tions, and for use of the secondary bus when forwarding downstream transactions. the arbiter for the primary bus resides external to pci 6254, typically on the motherboard. for the secondary pci bus, pci 6254 implements an internal arbiter. this arbiter can be disabled, and an external arbiter can be used instead. this chapter describes primary and secondary bus arbitration. 12.1 primary pci bus arbitration pci 6254 implements a request output pin, p_req#, and a grant input pin, p_gnt#, for primary pci bus arbitration. pci 6254 asserts p_req# when forwarding transa ctions upstream; that is, it acts as initiator on the primary pci bus. as long as at least one pending transac tion resides in the queues in the upstream direction, either posted write data or delayed tr ansaction requests, pci 6254 keeps p_req# asserted. however, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by pci 6254 on the primary pci bus, pci 6254 deasserts p_req# for two pci clock cycles. for all cycles through the bridge, p_req# is not asserted until the transaction request has been completely queued. if p_gnt# is asserted (by the primary bus arbiter afte r pci 6254 has asserted p_req#), pci 6254 initiates a transaction on the primary bus during the next pci clock cycle. when p_gnt# is asserted to pci 6254 when p_req# is not asserted, pci 6254 parks p_ad, p_cbe, and p_par by driving them to valid logic levels. when the primary bus is parked at pci 6254 and pci 6254 then has a transaction to initiate on the primary bus, pci 6254 starts the transaction if p_gnt# wa s asserted during the previous cycle. 12.2 secondary pci bus arbitration pci 6254 implements an internal secondary pci bus arbiter. this arbiter supports nine external masters in addition to pci 6254. the internal arbiter can be dis abled, and an external arbiter can be used instead for secondary bus arbitration. 12.2.1 secondary bus arbitrati on using the internal arbiter to use the internal arbiter, the secondary bus arbite r enable pin, s_cfn#, must be tied low. pci 6254 has nine secondary bus request input pins, s_req#[8:0], and ni ne secondary bus output grant pins, s_gnt#[8:0], to support external secondary bus masters. the secondary bus request and gr ant signals are connected internally to the arbiter and are not brought out to external pins when s_cfn# is high. each group can be programmed to use a rotating priority or a fixed priority scheme, through configuration register 50h. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 110 12.2.1.1 rotating priority scheme the second a r y arbite r sup ports a p r og rammabl e 2-l e vel ro tating al gorithm th at take s care of 10 re que sts/g r ants, inclu d ing the pci 6254. fi gure 1 2?1 sh ows an exam ple of an inte rnal a r biter where fou r ma sters, inclu d i ng pci 6254, a r e in the high p r i o rity gro up, and six mast ers are in th e low p r io rity grou p. usin g this exam p l e, if all requ est s a r e alway s a s sert ed, the high e s t p r iority rota tes a m ong th e ma sters i n t he follo win g f a shi on (hig h prio rity members are given in italics, low pr iority membe r s, in boldfa c e type ): b, m0, m1, m2, b, m0, m1, m3, b, m0, m1, m4, b, m0, m1, m5, and so on. b m0 m1 m2 lpg m3 m4 m5 m6 m7 m8 figure 12-1 secondary arbiter example if all the masters a r e a ssi gned to on e grou p, the al gorithm d e fa ults to a rotat i ng prio rity among all the maste r s. after reset, a ll external masters are assign ed to the low prio rity grou p, and pci 6254 is a ssi gne d to the high prio rity grou p . pci 6254 receive s hi gh est pri o rity o n the targ et bus every ot her tran sa ction, and prio ri ty rotates evenly amon g the other m a sters. prioritie s are reevalu a ted e v ery time s_ frame# i s a s serted, that is, at th e start of ea ch ne w tran sa ction on the se con dary p c i bus. from this point un til the time th at the next transac tion s t arts , t he arbite r asse rts the grant sign al co rre spondi ng to the highe st prio rity reque st that is asse rte d . if a grant for a pa rticula r req u e s t is asserted , and a highe r prio rity requ e s t su bsequ en tly asse rts, th e arbi te r de a s sert s the a s serte d g r ant sign al and assert s the grant co rrespondi ng to t he ne w hi gh er p r io rity re que st on th e next pci clo ck cycl e. whe n p r ioriti es a r e reevalu a ted, the high est pri o rity is assi g ned to the ne xt highest pri o rity master relative to the maste r that initiated the previo us transactio n . the ma ster t hat initiated the la st tran saction now h a s the lo we st prio rity in its grou p. priority is also re-evaluate d if the requ esting ag ent dea sserts its requ est with o u t gener ating any cycles while it wa s gra n ted. if pci 6254 detects that an initiator has failed to assert s_frame# after 16 cycl es of both grant assertio n and a secondary idl e bus condition, the ar biter will re-evaluat e grant assi gnment. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 111 b, m0, m1, m2, m7, m8, m3, m4, m5, m6 x x x 12.2.1.2 fixed priority scheme pci 6254 also has support for a fixed priority scheme within the two priority groups. in this case, configuration register 50h, bit 0 and 2 controls whethe r the low priority group or the high prio rity group will use fixed or rotating priority scheme. if a fixed priority scheme is used, then a master within the group is assigned to have the highest priority within its group, and then an option is set to cont rol the priority of other mast ers relative to the highest priority master. this is controlled through bits 4-11 and bi ts 1 and 3 of the internal arbiter control register (reg. 50h). for example, using the previous example with the groups at fixed priority, if master 7 has the highest priority of the low priority group, and pci 6254 has the highest priori ty of the high priority group, and priority decreases in ascending order of masters for both group s, (bits 1,3 of register 50 are set to 1). the order of priority with the highest first, will be as follows: if bits 1, 3 or register 50 are set to 0, priority will decrease in the othe r direction, so t he order becomes: b, m2, m1, m0, m7, m6, m5, m4, m3, m8 to prevent bus contention, if the sec ondary pci bus is idle, the arbiter never asserts one grant signal in the same pci cycle in which it deasserts another. it deasserts one grant, and then asserts the next grant, no earlier than one pci clock cycle later. if the secondary pci bus is busy, that is, either s_frame# or s_irdy# is asserted, the arbiter can deassert one grant and assert anot her grant during the same pci clock cycle. 12.2.2 secondary bus arbitrati on using an external arbiter the internal arbiter is disabled when the secondary bus central function control pin, s_cfn#, is tied high. an external arbiter must then be used. when s_cfn# is tied high, pci 6254 reconfigures two pins to be external request and grant pins. the s_gnt#[0] pin is reconfigured to be the pci 6254?s external request pin because it is output. the s_req#[0] pin is reconfigured to be the external gr ant pin because it is input. when an external arbiter is used, pci 6254 uses the s_gnt#[0] pin to request the secondary bus. when th e reconfigured s_req#[0] pin is asserted low after pci 6254 has asserted s_gnt#[0], pci 6254 initiates a tran saction on the secondary bus one cycle later. if grant is asserted and pci 6254 has not asserted the request, pci 6254 parks the ad, cbe and par pins by driving them to valid logic levels. the unused secondary bus grant outputs, s_gnt#<8:1> ar e driven high. unused secondary bus request inputs, s_req#<8:1> should be pulled high. 12.2.3 internal arbitration parking if the internal secondary bus arbiter is enabled, the secon dary arbiter can be optionally parked at the last active slot, or on any of the designated slots, and it can also be disabled. pci 6254 has the following options related to arbitration parking: no parking: all grants are deasserted if there are no requests asserted. fixed parking: grant can be assigned to a specified master. last master granted: grant is assign to the last granted master. these options are selected through internal arbiter control register at 50h, bits 12-15. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 112 13 general purpose i/o interface the pci 6254 implements a 16 general-purpose i/o (gpi o) interface pins. during normal operation, the configuration registers control gpio in terface. in addition, the gpio pins can be used for the following functions: x during secondary reset, the gpio interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. x a live insertion bit can be used, along with the gpio [3] pin, to bring the pci 6254 gracefully to a halt through hardware, permitting live insertion of option cards behind the pci 6254. x during non-transparent mode, some pins can be used as an interrupt for communication between the primary and secondary interfaces. table 13-1: gpio pin alternate functions gpio pin alternate function gpio0 ? pull-up functions as shift register clock output when prst# asserted. gpio1 ? pull-up gpio2 ? pull-up functions as shift/load control out put to shift register when prst# asserted gpio3 ? pull-up can be used for live insertion functi on, if set as input and live insertion mode bit is set. if high, transaction forwarding is disabled. gpio4 ? pull-up if non-transparent mode is enabled, this input can be used as an active low level triggered external interrupt input to trigger p_inta#. gpio5 ? pull-up if non-transparent mode is enabled, this input can be used as an active low level triggered external interrupt input to trigger s_inta#. gpio6 ? pull-up gpio7 ? pull-up gpio8 power up pwrgd latched status gpio9 power up pwrgd latched status gpio10 power up pwrgd latched status gpio11 power up pwrgd latched status gpio12 power up pwrgd latched status gpio13 power up pwrgd latched status gpio14 power up pwrgd latched status gpio15 power up pwrgd latched status * important: internal pull-low resistor is weak a nd when pull-low function is used, an external pull-low resistor is recommended. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 113 13.1 gpio control registers during normal operation, the gpio interface is cont rolled by the following co nfiguration registers: x the gpio output data register x the gpio output enabl e control register x the gpio input data register gpio7-0 consist of five 8-bit fields: x write-1-to-set output data field x write-1-to-clear output data field x write-1-to-set signal output enable control field x write-1-to-clear signal output enable control field x input data field the output enable fields control whether each gpio signal is input or output. each signal is controlled independently by a bit in each output enable control field. if a 1 is written to the write-1-to-set field, the corresponding pin is activated as an output. if a 1 is written to the write-1-to-clear field, the output driver is three- stated, and the pin is then input only. writing zeros to t hese registers has no effect. the reset state for these signals is input only. the input data field is read only and reflects the current value of the gpio pins. a type-0 configuration read operation to this address is used to obt ain the values of these pins . all pins can be read at any time, whether configured as input only or as bi-directional . the output data fields also use the write-1-to-set and write-1-to-clear method. if a 1 is wr itten to the write-1-to-set field and the pin is enabled as an output, the corresponding gpio output is driven high. if a 1 is written to the write-1-to-clear field and the pin is enabled as an output, the corresponding gpio output is driven low. writing zeros to these registers has no effect. the value written to the output register will be driven only w hen the gpio signal is configured as output. type-0 configuration write operation is used to program th ese fields. the reset value for the output is 0. gpio15-8 consist of three 8-bit fields: x write- 0/1 as output data field x write- 0/1 to disable/enable output enable control field x input data field pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 114 14 clocks this chapter provides information about the clocks. 14.1 primary and secondary clock inputs pci 6254 implements a separate clock input for each pci inte rface. the primary interface is synchronized to the primary clock input, p_clkin, and the secondary interface is synchronized to the secondary clock input, s_clkin. pci 6254 operates at a maximum frequency of 66 mhz. ou tput clocks s_clk[9:0] can be derived from p_clkin either at the same frequency, at p_clki n / 2, or at an asynchronous frequency. pci 6254 primary and secondary clock inputs can be as ynchronous. the skew between p_clkin and s_clkin is irrelevant. pci 6254 can tolerate a 1:2.5 or 2.5:1 frequency ratio between primary and secondary clock inputs. 14.2 secondary clock outputs pci 6254 has 10 secondary clock outputs that can be used as clock inputs for up to nine external secondary bus devices with one feedback to s_clkin. the rules for using secondary clocks are: x each secondary clock output is limited to no more than 1 pci load. x all clock trace length, including feedback clock to the pci 6254, must have equal length and impedance. x terminating or disabling unused secondary clock outputs is recommended to reduce power dissipation and noise in the system. 14.3 disabling unused secondary clock outputs when secondary clock outputs are not used, both gpio[3:0] and msk_in can be used to clock in a serial mask that selectively three-stat es secondary clock outputs. see gpio sect ion for details in this application. after the serial mask has been shifted into the pci 6254, the value of the mask is readable and can be changed in the secondary clock disable mask register. when the mask is modified by a configuration write operation to this register, the new clock mask disables the appropriate se condary clock outputs within a few cycles. this feature allows software to disable or enable secondary clock out puts based on the presence of option cards, and so on. pci 6254 delays deasserting the secondary reset signal, s_rstout#, until the serial clock mask has been completely shifted in and the secondary clocks have been disabled or enabled, according to the mask. the delay between p_rstin# assertion and s_rsto ut# deassertion is 16 cycles (32 cy cles if s_clk is operating at 66mhz). pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 115 14.3.1 secondary clock control the pci 6254 uses the gpio pins and the mskin signal to input a 16-bit serial data st ream. this data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs. the serial data stream is shifted in as soon as p_rstin# is detected deasserted and the secondary reset signal, s_rstout#, is detected asserted. the deassertion of s_rstout# is delayed until the pci 6254 completes shifting in the clock mask data, which takes 16 clock cycl es (32 cycles if operating at 66 mhz). after that, the gpio pins can be used as general purpose i/o pins. an external shift register should be used to load and sh ift the data. the gpio pins are used for shift register control and serial data input. the data is input through the dedicated input signal, mskin. the shift register circuitry is not necessary for correct operation of the pc i 6254. the shift registers can be eliminated, and mskin can be tied low to enable all secondary clock outputs or tied high to force all secondary clock outputs high. gpio shift register operation gpio pin operation gpio[0] shift register clock output at 33 mhz maximum frequency. gpio[2] 0 1 load shift shift register control: gpio serial data format bit description sclk_o output [1:0] slot 0 prsnt#<1:0> or device 0 0 [3:2] slot 1 prsnt#<1:0> or device 1 1 [5:4] slot 2 prsnt#<1:0> or device 2 2 [7:6] slot 3 prsnt#<1:0> or device 3 3 [8] device 4 4 [9] device 5 5 [10] device 6 6 [11] device 7 7 [12] device 8 8 [13] can be used for pci 6254 s_clkin input 9 [14] reserved not applicable [15] reserved not applicable the first eight bits contain the prsnt#[1:0] signal values for four slots, and these bits control the sclko[3:0] outputs. if one or both of the prsnt#[1:0] signals are 0, that indicates that a card is present in the slot and therefore the secondary clock for that slot is not mask ed. if these clocks are connected to devices and not to slots, one or both of the bits should be tied low to enabl e the clock. the next five bits are the clock mask for devices; each bit enables or disables the clock for one dev ice. these bits control t he sclko[8:4] outputs: 0 enables the clock, and 1 disables the cloc k. bit 13 is the clock enable bit for sclko[9], which is connected to the pci 6254?s sclkin input. if desired, the assignment of sclko clock outputs to slots, devices, and the pci 6254?s sclkin input can be rearranged fr om the assignment shown here. however, it is important that the serial data stream format match the assignme nt of sclko outputs. the gpio pin serial protocol is designed to work with two 74f166 8-bit shift registers. 14.3.2 force s_clk[9:0] to low there is also the s_clkoff input. when this pin is tied high, all s_clk[9:0] will be disabled and driven low. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 116 14.4 using an external clock source pci 6254 has 2 signals, osc_sel# and osc_in which can be used to connect an external clock source to the pci 6254. during normal operation, pci 6254 generates s_ clk[9:0] outputs based on the pci clk source. if oscsel# is low, pci 6254 will derive s_ clk[9:0] outputs from the oscin signal instead. clock division will still be performed on the oscin clock depending on the st ates of the p_m66en and s_m66en signals. pci 6254 also has s_clk_stb input allowing designer to i ndicate the secondary external clock source is stable. if this input is 0 indicating that the s_clkin is not yet stable, the pci 6254 will not let s_rstout# deassert. 14.5 frequency division options in transparent mode, the pci 6254 has built-in frequency division options to automatically adjust the output clocks s_clk[9:0] for 66mhz or 33mhz operations. the following table depicts division conditions. p_m66en s_m66en division 1 1 1/1 1 0 1/2 0 1 1/1 0 0 1/1 notes 1. s_m66en pin cannot be floating. 2. in revision aa, the pci 6154 does not driv e s_m66en to low when p_m66en is low. 3. in revision ab, the pci 6154 drives s_m66en to low when p_m66en is low. 14.6 running secondary port faster than primary port pci 6254 allows running the secondary port at a fa ster rate than the primary port. pci 6254 a synchronous design supports standard 66mhz to 33mhz and faster seconda ry port speed such as 33mhz to 66mhz conversion. designers must provide the faster clock source either through an oscillator or a clock generator. if oscin is used to make use of the sclkn outputs, t he division control can be disabled by pulling the s_m66en pin high and not connecting this pin to the pci slots. otherwise extern al clock can be fed direct ly into the s_clkin. 14.7 universal mode clock behavior there are some changes in clock behavior when pci 6254 is in universal mode. pin descriptions s_clkin during universal non-transparent mode (u_m ode = 1 and trans# = 1). this input is ignored by pci 6254 and the internal logic uses the input clock from the s_clk0 pin. s_clk0 acts as an input pin to provide clock for the secondary interface. s_clk0 s_clk0 output is three-stated during universal non-transparent mode. this allows s_clk0 to take the clk signal from a cpci back plane for the secondary port logic. when in cpci system slot, s_clk0 drives the cpci. when in peripheral slot, back plane clock drives s_clk0 pin. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 117 x x x 15 frequency operation pci 6254 supports up to 66 mhz operations. cfg66 and pm66en pin inputs should be high for 66mhz operation. 15.1 66-mhz operation signal cfg66 must be tied high on the board to enable 66mhz operation and to set the 66mhz capable bit in the status register and the secondary status register in configuration space. signals p_m66en and s_m66en indicate whether the primary and secondary interfaces, respectively are operating at 66mhz. this information is needed to control t he frequency of the secondary bus. note that the pci local bus specification, revision 2. 2 restricts clock frequency changes abov e 33mhz to during pci reset only. the following primary and secondary bus frequency combinations are supported when using the primary p_clkin to generate the se condary clock outputs: 66mhz primary bus, 66mhz secondary bus 66mhz primary bus, 33mhz secondary bus 33mhz primary bus, 33mhz secondary bus if p_m66en is low (66mhz capable, primary bus at 33mhz ), then the pci 6254 drives low s_m66en to indicate that the secondary bus is operating at 33mhz. if designers want to run the secondary bus at faster than primary bus, s_m66en need not be connected to secondary pci devices. pci 6254 can also generate s_clk outputs from the oscin input if enabled. when pci 6254 is running with external clock input that is not generated from s_cl k[9:0] outputs, the p_m66en and s_m66en controlled clock division will not apply. when oscin or other external clock inputs are used for the secondary port, pci 6254 can run with a maximum ratio of 1:2.5 or 2.5:1 between pr imary and secondary bus clocks. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 118 16 reset this chapter describes the primary interface, secon dary interface, and chip reset mechanisms. pci 6254 has three reset inputs, pwrgd, p_rstin# and s_rstin#. th ere are also power management initiated internal reset and software controlled internal reset. note: after any of the resets are deasserted, pci 6254 requ ires 32 clocks to initialize the bridge functions. great care must be exercis ed when using p_rstout# and s_ rstout# to feed to their corresponding rstin#. as p_rstin# can c ause s_rstout# and s_rstin# can cause p_rstout#, there is a latching e ffect if both feedbacks are applied. 16.1 power good reset for pci 6254, a clean 3.3v pwrgd input signal must be provided. this input should not be simply connected to the 3.3v supply. when pwrgd is low, the following events occur: x registers 80h-ffh and exte nded registers that have default values are reset. x all outputs are three-stated and all internal logic are reset. (this is not true for pci 6254 rev aa) x (pci 6254 rev aa only: in non-transparent mode, pwrgd going high causes eeprom to be loaded.) important: pci 6254 requires a clean low to high transition pwrgd input. the pwrgd is not internally debounced. it must be debounced externally and a high input must reflect that the power is indeed stable. its asserting and deasserting edges can be asynchronous to p_clk and s_clk. 16.1.1 pwrgd and output signals except for pci 6254 rev aa, as soon as pwrgd is 0, all outputs, including all clock and reset outputs, are three- stated. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 119 16.2 primary reset input pci 6254 requires at least 2 clocks before p_rstin# rising edge to reset properly. when p_rstin# is asserted, the following events occur: x in both transparent and non-transparent modes, pci 6254 three-states all primary pci interface signals, except s_rstout#, s_gnt#[8:0], sclko[9:0], and s_re q64#, within 1 clock. in non-transparent mode, s_req64# is also three-stated with 1 clock. x in non-transparent mode, primary configuration registers 0-3fh, secondary configuration registers 0-3fh, and shadow registers 40h-7fh are reset. in transparent mode, all registers, except st icky registers, are reset. x in non-transparent mode, s_rstout# is driven active to indicate a primary pci reset if the secondary reset output mask bit is not set. x in non-transparent mode, upon deassertion of p_rstin# , s_inta# is driven active and status bit set if the primary pci interrupt event is enabled. x in non-transparent mode, pci 6254 performs a primary po rt state machine reset only if the secondary reset output mask bit at register d9h bit 3 is not se t. secondary port state machines are not affected. x in transparent mode, active p_rstin# will cause se condary port reset. 43 clocks after p_rstin# going high, s_rstout# will go high. x clock disable bits begin to be shifted in at the rising edge of p_rstin#. the p_rstin# asserting and deasserting edges can be asynchronous to p_clk and s_clk. pci 6254 requires 32 primary port pci clocks after p_rstin# rising edge to reset its internal logic. when p_rstin# is asserted, all posted write and delay ed transaction data buffers are reset; therefore, any transactions residing in buffers at the ac tive time of p_rstin# are discarded. 16.3 primary reset output only in non-transparent mode would pci 6254 assert p_ rstout# when any of the following conditions is met: x secondary reset input (using s_rstout# pin) is asserted in universal non-transparent mode (u_mode = 1, trans# = 1). x s_rstin# is asserted in standard non-transparent mode with primary port having boot priority (trans# = 1, p_boot = 1). signal p_rstout# remains asserted as long as s_rstin# is asserted. x the primary reset bit in the non-transparent diagnostic control register is set. signal p_rstout# remains asserted until the reset control bit is cleared. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 120 16.4 secondary reset input s_rstin# input pin is only used for non-transparent oper ations and is not used in transparent or universal mode. in universal non-transparent mode, s_rstout# pin is used as the secondary port reset input pin. pci 6254 requires 2 clocks before s_rstin# rising edge to reset properly. when s_rstin# is asserted, the following events occur: x pci 6254 three-states all secondary pci interface si gnals, except s_rstout#, s_gnt#[8:0], sclko[9:0], and s_req64# within 1 clock. x non-transparent mode secondary c onfiguration registers 0-3fh are not reset. there are no registers that are reset by an s_rstin# active input. x p_rstout# is driven active to indicate a secondary pc i reset if the primary reset output mask bit is not set. x upon deassertion of s_rstin#, p_inta# is driven active and status bit set if the secondary pci interrupt event is enabled. x pci 6254 performs a secondary port state machine reset only. primary port state machine are not affected. the s_rstin# asserting and deasserting edges can be asynchronous to p_clk and s_clk. pci 6254 requires 32 secondary port pci clocks to reset its internal logic. important: when not used, s_rstin# must be connected to high state. when s_rstin# is asserted, all sec ondary pci interface signals, including the secondary grant outputs, are immediately three-stated. all posted write and delayed transaction data buffers are reset; therefore, any transactions residing in buffers at the ac tive time of s_rstin# are discarded. when s_rstin# is asserted by means of the secondary reset bit (bit 6 of register 3eh in transparent mode and 42h in non-transparent mode), pci 6254 c onfiguration space remains accessible from the primary interface. in transparent mode and universal transparent mode, se condary port reset is automatic whenever s_rstout# is active. s_rstin# input is not used and it should be tied ?high?. 16.4.1 universal mode secondary reset input in universal non-transparent mode (u_mode = 1, trans# = 1), s_rstout# output is disabled and s_rstout# pin is used as the equivalent of s_rstin# i nput pin. during this mode, a ?low? input presented at s_rstout# pin will cause a secondary por t reset. s_rstin# input is not used. 16.5 secondary reset output pci 6254 asserts s_rstout# when any of the following conditions is met: x signal p_rstin# is asserted. signal s_rstout# remains asserted as long as p_ rstin# is asserted and does not deassert until p_rstin# is deasserted, or while the secondary clock seri al disable mask is being shifted in (16 clock cycles after p_rstin# deassertion) or the secondary clock input stable s_clkin_stb input is ?low?. x the secondary reset bit in the bridge control register is set. signal s_rstout# remains asserted until the rest control bit is cleared. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 121 16.6 software chip reset the chip reset bit (transparent mode register 41h an d non-transparent mode register d9h, bit 0) in the diagnostic control register can be used to reset the enti re pci 6254 like the pwrgd input except that it will not cause p_rstout# or s_rstout# to go active and it will not three-states the signals. however it will cause an eeprom autoload if pci 6254 is in non-transparent mode. when the chip reset bit is set, all registers and chip state are reset. within 4 pci clock cycles after completion of the configuration write operation that sets the chip reset bi t, the chip reset bit automatically clears and the chip is ready for configuration. during chip reset, pci 6254 is inaccessible. 16.7 power management internal reset in transparent mode, or in non-transparent mode with p_ boot = 0, when there is a d3hot to d0 transition with power management control registers bit 1:0 programmed to d0, an internal reset equivalent to p_rst input will be generated and all relevant registers will be reset. however p_rstout# and s_rstout# will not be active. in non-transparent mode and p_boot = 1, when there is a d3hot to d0 transition with power management control registers bit 1:0 programmed to d0, the p_rstout# will not be active. 16.8 reset to first cycle access latency the pci 6254 supports eeprom initialization and needs time to determi ne if eeprom data is valid before allowing the first cycle access to its registers, with t he exception of test register 52h. during eeprom loading, all access to pci 6254 will be retried. test register 52h can be accessed within the first 128 2 pci clocks upon p_rstin# going high in transparent mode and upon pwrgd going high in non-transparent mode. subsequent eeprom loading can be stopped if a configuration write can be co mpleted within these 1282 clocks. eeprom loading speed can also be accelerated by a factor of 32 times setting register 52h bit 1 to 1 with these 1282 clocks. the following calculation is based on eeprom cl ock speed being pci clo ck speed divided by 1024. in transparent mode, upon p_rstin# going high, the pc i 6254 requires 56836 pci clocks to determine if the eeprom signature is valid. if the signature is not valid, the pci 6254 will stop eepr om load and access to pci 6254 registers can begin. if t he signature is valid, the pci 6254 needs 9216 clocks to load each eeprom register until the specified registers are completely loaded. in non-transparent mode, upon pwrgd going high, the pci 6254 requires pci 56836 clocks to determine if the eeprom signature is valid. if the signature is not valid, the pci 6254 will stop eeprom load and access to pci 6254 registers can begin. if the signature is valid, the pci 6254 needs 9216 clocks to load each eeprom register until the specified r egisters are completely loaded. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 122 16.9 reset inputs table there are transparent or non-transparent mode related rese t controls that can be used to generate primary or secondary reset outputs, as shown in the table below. the following table depicts the effect of different pci 6254 reset input sources. operating mode reset inputs transparent mode non-transparent mode universal transparent mode universal non-transparent mode (s_rstout# used as secondary reset input) p_rstin# - resets primary and secondary ports - causes s_rstout# active - causes eeprom load - resets only primary port - causes s_rstout# active - resets primary and secondary ports - causes s_rstout# active - causes eeprom load - resets only primary port s_rstin# - not used - resets only secondary port - causes p_rstout# active - not used - not used s_rstout# - not used as input - not used as input - not used as input - used as reset input and resets only secondary port - causes p_rstout# active s_clk_stb not active - resets only secondary port - causes s_rstout# active - resets only secondary port - causes s_rstout# active - resets only secondary port - causes s_rstout# active - no effect pwrgd not ready - resets sticky registers - resets sticky registers - causes eeprom load - resets sticky registers - resets sticky registers - causes eeprom load register 41h bit 0 chip reset - resets internal state machines - na - resets internal state machines - na register d9h bit 0 chip reset - na - resets internal state machines - causes eeprom load - na - resets internal state machines - causes eeprom load register 3eh bit 6 secondary reset - resets only secondary port - causes s_rstout# active - na - resets only secondary port - causes s_rstout# active - na shadow register 42h bit 6 secondary reset - na - causes s_rstout# active - na - no effect register d9h bit 5 primary port software reset - na - causes p_rstout# active - na - causes p_rstout# active pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 123 16.10 power up and reset pin state table there are powergood, p_rstin#, s_rstin# and device hiding support in the pci 6254. the following depicts the pin state for each of such event. pci 6254 rev aa table is listed is section 17.10.1. legend: u = undermined i = input only t = three-stated d1 = drive 1 to output d0 = drive 0 to output d01 = can drive both 0 or 1 to output power up / reset pci 6254 pins pwrgd = 0 with or without clock trans mode p_rstin # = 0 non-trans mode p_rstin# = 0 s_rstin# = 0 non-univ non-trans mode s_rstin# = 0 p_rstin# = 1 univ non-trans mode s_rstin# = 0 p_rstin# = 1 device hiding ejector switch open p_rstin# = 1 s_rstin# = 1 p_ad[63:0] t t t t t p_cbe[7:0] t t t t t p_par t t t t t p_par64 t t t t t p_frame# t t t t t p_irdy# t t t t t p_trdy# t t t t t p_devsel# t t t t t follows the corresponding modes value to the left except for difference listed below p_stop# t t t t t p_lock# t t t t t p_idsel i i i i i p_perr# t t t t t p_serr# t t t t t p_req# t t t d1 d1 p_gnt# i i i i i p_m66en# i i i i i p_req64# t t t t t p_ack64# t t t t t p_inta# t t t t t s_ad[63:0] t t t t t s_cbe[7:0] t t t t t s_par t t t t t s_par64 t t t t t s_frame# t t t t t s_irdy# t t t t t s_trdy# t t t t t s_devsel# t t t t t s_stop# t t t t t s_lock# t t t t t s_idsel i i i i i s_perr# t t t t t s_serr# t t t t t s_req0# i i i i d1 s_gnt0# t d1 d1 d1 i s_req[8:1]# i i i i i s_gnt[8:1]# t d1 d1 d1 d1 s_m66en# i i i i i s_req64# t d0 t t t s_ack64# t t t t t s_inta# t t t t t pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 124 s_rstin# = 0 s_rstin# = 0 power up / reset pci 6254 pins pwrgd = 0 with or without clock trans mode p_rstin # = 0 non-trans mode p_rstin# = 0 non-univ non-trans mode s_rstin# = 0 p_rstin# = 1 univ non-trans mode p_rstin# = 1 device hiding ejector switch open p_rstin# = 1 s_rstin# = 1 p_clkin i i i i i s_clkin i i i t i -not used s_sclk0 -s_clkoff=0 -s_clkoff=1 t t d01 d0 d01 d01 d0 d0 i i s_clk[9:1] -s_clkoff=0 -s_clkoff=1 t t d0 d0 d01 d01 d0 d01 d0 d01 s_clkoff i i i i i s_clkin_stb i i i i i msk_in i i i i i oscsel# i i i i i oscin i i i i i pwrgd i i i i i p_rstout# t d1 d0 d0 d0 d1 p_rstin# i i i i i s_rstout# t d0 d0 d01 i d1 i in univ non-trans mode s_rstin# i i i i i enum# t t t t t l_stat -eject_en#=0 t d1 d1 d01 d01 d0 eject i i i i i eject_en# i i i i i s_cfn# i i i i i cfg66 i i i i i bpcc_en i i i i i gpio0 t d1 d0 d01 d01 t -if not used as output gpio1 t d0 d0 d01 d01 t -if not used as output gpio2 t d0 d0 d01 d01 t -if not used as output gpio[15:3} t t t t t p_pme# t t t t t s_pme# t t t t t eepclk t d1 d1 d1 d1 eepdata t d1 d1 d1 d1 ee_en# i i i i i 64en# i i i i i trans# i i i i i u_mode i i i i i test# i i i i i xb_mem i i i i i s_idsel i i i i i p_boot i i i i i pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 125 16.10.1 pci 6254 rev aa power up and reset pin state table in rev. aa, power good input does not affect pin stat e. p_rstin and valid clock are required to reach known initial pin state. power up / reset pci 6254 pins non-trans mode non-univ non-trans mode p_rstin# = 1 trans mode p_rstin # = 0 p_rstin# = 0 s_rstin# = 0 s_rstin# = 0 p_rstin# = 1 univ non-trans mode s_rstin# = 0 p_rstin# = 1 device hiding ejector switch open s_rstin# = 1 p_ad[63:0] t t t t p_cbe[7:0] t t t t p_par t t t t p_par64 t t t t p_frame# t t t t p_irdy# t t t t p_trdy# t t t t p_devsel# t t t t follows the corresponding modes value to the left except for difference listed below p_stop# t t t t p_lock# t t t t p_idsel i i i i p_perr# t t t t p_serr# t t t t p_req# t t d1 d1 p_gnt# i i i i p_m66en# i i i i p_req64# t t t t p_ack64# t t t t p_inta# t t t t s_ad[63:0] t t t t s_cbe[7:0] t t t t s_par t t t t s_par64 t t t t s_frame# t t t t s_irdy# t t t t s_trdy# t t t t s_devsel# t t t t s_stop# t t t t s_lock# t t t t s_idsel i i i i s_perr# t t t t s_serr# t t t t s_req0# i i i d1 s_gnt0# d1 d1 d1 i s_req[8:1]# i i i i s_gnt[8:1]# d1 d1 d1 d1 s_m66en# i i i i s_req64# d0 t t t s_ack64# t t t t s_inta# t t t t pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 126 s_rstin# = 0 power up / reset pci 6254 pins trans mode p_rstin # = 0 non-trans mode p_rstin# = 0 s_rstin# = 0 non-univ non-trans mode s_rstin# = 0 p_rstin# = 1 univ non-trans mode p_rstin# = 1 device hiding ejector switch open p_rstin# = 1 s_rstin# = 1 p_clkin i i i i s_clkin i i t i -not used s_sclk0 -s_clkoff=0 -s_clkoff=1 d01 d0 d01 d0 d01 d0 i i s_clk[9:1] -s_clkoff=0 -s_clkoff=1 d01 d0 d01 d0 d01 d0 d01 d0 s_clkoff i i i i s_clkin_stb i i i i msk_in i i i i oscsel# i i i i oscin i i i i pwrgd i i i i p_rstout# d1 d0 d0 d0 d1 p_rstin# i i i i s_rstout# d0 d0 d1 i d1 i in univ non-trans mode s_rstin# i i i i enum# t t t t l_stat -eject_en#=0 d1 d1 d01 d01 d0 eject i i i i eject_en# i i i i s_cfn# i i i i cfg66 i i i i bpcc_en i i i i gpio0 d0 d0 d01 d01 t -if not used as output gpio1 d0 d0 d01 d01 t -if not used as output gpio2 d0 d0 d01 d01 t -if not used as output gpio[15:3} t t t t p_pme# t t t t s_pme# t t t t eepclk d1 d1 d1 d1 eepdata d1 d1 d1 d1 ee_en# i i i i 64en# i i i i trans# i i i i u_mode i i i i test# i i i i xb_mem i i i i s_idsel i i i i p_boot i i i i pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 127 17 bridge behavior a pci cycle is initiated by asserting the frame# signal. in a br idge, there are a number of possibilities. these are summarized in the table below. table 17-1 show s pci 6254?s actions for different cycle types. table 17-1: bridge actions for various cycle types initiator target response master on primary target on primary pci 6254 does not respond. it detects this situation by decoding the address as well as monitoring the p_devsel# for other fast and medium devices on the primary port. master on primary target on secondary pci 6254 as serts p_devsel#, terminate the cycle normally if able to posted, otherwise return with a retry. then passes the cycle to the appropriate port. when cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. master on primary target not on primary nor secondary port pci 6254 does not respond and the cycle will terminate as master abort. master on secondary target on the same secondary port pci 6254 does not respond. master on secondary target on primary or the other secondary port pci 6254 asserts s_devsel#, terminate the cycle normally if able to posted, otherwise return with a retry. then passes the cycle to the appropriate port. when cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. master on secondary target not on primary nor the other secondary pci 6254 does not respond. a target then has up to three cycles to respond before su btractive decoding is initiat ed. if the target detects an address hit, it should assert its devsel# signal in the cycle corresponding to the values of bits 9 and 10 in the configuration status register. termination of a pci cycle can occur in a number of ways . normal termination begins by the initiator (master) deasserting frame# with irdy# being asserted (or remain ing asserted) on the same cycle. the cycle completes when trdy# and irdy# are both asserted simultaneously. the target should deassert trdy# for one cycle following final assertion (sustained three-state signal). 17.1 abnormal termination (initiated by bridge master) 17.1.1 master abort master abort indicates that pci 6254 acting as a ma ster receives no response (i.e., no target asserts p_devsel# or s_devsel#) from a ta rget. the bridge deasserts fram e# and then deasserts irdy#. 17.2 parity and error reporting parity must be checked for all addresses and write data. parity is defined on the p_par/p_par64 and s_par/s_par64 signals. parity should be even (i.e. an even number of ?1?s) across ad, cbe, and par. parity information on par is valid the cycle after ad and cbe are valid. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 128 s_ad[31:16] 17.2.1 reporting parity errors for all address phases, if a parity error is detected, t he error is reported on the p_serr# signal by asserting p_serr# for one cycle and then three-stating two cycl es after the bad address. p_serr# can only be asserted if bit 6 and 8 in the command register are both set to 1. for write data phases, a parity error is reported by asserting the p_perr# signal two cycles after the data phase and should remain asserted for one cycle when bit 8 in the command register is set to a 1. the target reports any type of data parity erro rs during write cycles, while the master reports data parity errors during read cycles. detection of an address parity error will cause the pci bridge target to not claim the bus (p_devsel# remains inactive) and the cycle will then terminate with a master abort. when the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a master abort. 17.3 secondary idsel mapping when pci 6254 detects a type-1 configuration transaction for a device connected to the secondary, it translates the type-1 transaction to type-0 transac tion on the downstream interface. ty pe-1 configuration format uses a 5- bit field at p_ad[15:11] as a device number. this is translated to s_ad[31:16] by pci 6254. table 18-2 explains how pci 6254 generates the secondary idsels. no device is permitted to connect idsel to ad[16] (the source bridge is device number 0). pci 6254 is the source bridge for its secondary bus. table 17-2: generation of s_idsel. p_ad[15:11] device number s_ad bit 0 0000b 0 0001b 0 0010b ? 0 1011b 0 1100b ? 0 1111b 1 xxxxb 0000 0000 0000 0001b 0000 0000 0000 0010b 0000 0000 0000 0100b ? 0000 1000 0000 0000b 0001 0000 0000 0000b ? 1000 0000 0000 0000b 0000 0000 0000 0000b 0 (source bridge) 1 2 ? 11 12 ? 15 special cycle 16 17 18 ? 27 28 ? 31 n/a 17.4 32-bit to 64-bit cycle conversion when a 32-bit device generates a request to a 64-bit pc i target, pci 6254 can optionally convert this cycle to a 64-bit cycle on the target bus. the conversion is only us ed on 32-bit prefetchable read memory cycles and posted memory write cycles with more than 2 data transfers. this function is set through bit 11 and 15 of register 46h . if the force 64-bit option is set, all posted memory write and prefetchable memory read cycl es are internally stored in the pci 6254 as 64-bit cycles if the data transfer will be more than 2 dwords cycles. these cycles execute on the target following the standard 64-bit pci protocol. pci 6254 asserts req64#, and if the target responds with ack64# active, pci 6254 will generate a 64-bit cycle. for memory write cycles, if the initial dword address is on an odd boundary, pci 6254 will generate a 64-bit cycle with a value of fh for the low dw ord of the initial write data transfer. if the target of a posted memory write is a 32-bit device, and it retries with data transfer on an odd dword boundary, the rest of the cycle will be completed later as a 32-bit cycle when pci 6254 retries it. otherwise, pci 62 54 will continue to re try the cycle as a 64-bit transaction. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 129 18 flow through optimization pci 6254 has several options that can be used to optimize pci transfers. during flow through posted write cycles, if there is only 1 data transfer pending in the internal post memory write queue, pci 6254 can be programmed to wait for a specified number of clocks before disconnecting. pci 6254 will deassert irdy# on the target side and wait for up to 7 clocks for more data from the initiator. if during this period new write data is received from the in itiator, pci 6254 will reas sert irdy# and cont inue with the write cycle. if no new write data is received during this period, the pci 6254 w ill terminate the cycle to the target with the last data from the queue and finish the cycle at a later time. for flow through delayed read cycles, if the internal read queue is almost full, pci 6254 can be programmed to wait for a specified number of clocks for read data from the target before disconnecting. during this time, the pci 6254 will deassert irdy# from the read source and wait for up to 7 clocks. if additional space becomes available in the read queue before the end of irdy# inactive period, pci 6254 will reassert irdy# and proceed with the next read data phase. if no additional space becomes available in the read queue, the current data phase will become the last one and the cycle will te rminate at the end of the data phase. 18.1 cautions with non-optimized pci master devices pci 6254 is capable of very high performanc e prefetching. however, for some pc i masters that cannot prefetch a lot of data due to limited buffers size or other reasons, the default aggressive prefetching may affect the overall performance. in this case, we recommend tuning pci 625 4 default aggressive prefet ching and require that the pci 6254 prefetching registers be programmed as the following: register in configuration space data 0x48 same value as in register 0x0c * * most pc set this value to 08h. 0x49 same value as in register 0x0c * * most pc set this value to 08h. 0x4a 0 0x4b 0 0x4c 0 0x4d 0 eeprom can also be used to progra m the configuration spac e upon reset. please refer to pci 6254 data book for detail description of each field. 18.2 read cycle optimization the main function is to increase t he probability of flow-through occurring during read access to prefetchable memory regions. in the case that flow-through does not oc cur, it would be inefficient for the pci 6254 to prefetch too little or too much data. if pci 6254 prefetches too li ttle and flow-through does not occur, then the read cycles become divided into multiple cycles. if pc i 6254 prefetches too much data and the internal fifo s fill, it has to wait for the initiator to retry the previous read cycle, and then flush unclaimed data before it can enqueue subsequent cycles. the prefetch count regi sters can be used to tune the pci 6254 for various pci masters. the initial count is equivalent to the cache line size, and assumes that a master will want at least 1 cache line of data. the incremental count is only used when pci 6254 does not detect flow-through for the current cycle being prefetched during the initial fetch count. pci 6254 will continue prefetching in increments until the maximum count is reached, then disconnect the cycle. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 130 x x x x x x mpc = maximum prefetch count this count controls the amount of data initially prefetched by the pci 6254 on the primary/secondary bus during reads to the prefetchable memory region. this assume s there is enough space in the internal fifo. if flow through is achieved during this initial prefetch, pci 6254 will continue prefetching beyond this count. 18.3 read prefetch boundaries for read prefetching, the pci 6254 implements several regist ers that control the amount of data prefetched on the secondary and primary pci bus. the following register s can be used to optimize pci 6254 performance during read cycles: primary initial prefetch maximum count primary incremental prefetch count primary maximum prefetch count secondary initial prefetch maximum count secondary incremental prefetch count secondary maximum prefetch count the pci 6254 will prefetch either until flow-through or until prefetch must stop based on the following conditions: (ipmc + ipc + ipc + ? + ipc) < mpc where ipc < ? mpc ipmc = initial prefetch maximum count ipc = incremental prefetch count if the prefetch count has not reached mpc and flow through has been achieved, the pci 6254 will keep on prefetching until the requesting master terminates the prefetch request. otherwise, when mpc has been reached, the pci 6254 will not prefetch any more. the incremental prefetch can be disabled by setting ipc >= mpc. 18.2.1 primary/secondary initial prefetch count 18.2.2 primary/secondary incremental prefetch count this register controls the amount of prefetching done afte r the initial prefetch. if flow-through was not achieved during the initial prefetch, pci 6254 will try to prefetch more data, until the fifo fills, or until the maximum prefetch count is reached. 18.2.3 primary/secondary maximum prefetch count this register limits the amount of pref etched data for a single entry available in the internal fifo at any time. during subsequent read prefetch cycles, the pci 6254 will disconnect the cycle when the count of data in the fifo for the current cycle reaches this va lue, and flow-through has not been achieved. for memory read and memory read line commands, pci 6254 prefetches from the starting address up until the address with offset equals to the initial prefetch count. for example, if initial prefetch count equals 20h and the starting address is 10h, pci 6254 will only prefetch 10h (20h-10h) count and afterward will start incremental prefetch until the maximum prefetch count is reached, or flow through is achieved. the exception is that if the initial prefetch count (ipc) and starting address offset difference (ipc ? starting address offset) is less than 3 transfers apart, the pci 6254 will not activate incremental prefetch. for memory read multiple commands, if the starting address is not 0, pci 6254 will first prefetch from the starting address up until the address with offset equals to the initial prefetch count. afterwards the pci 6254 will additionally prefetch one ?initial prefetch count? count. fo r example, if initial prefetch count equals 20h and the starting address is 10h, pci 6254 will first prefetch 10 h (20h-10h) count and then cont inues to prefetch another 20h count. afterwards, incremental prefetch is invoked until the maximum prefetch count is reached, or flow through is achieved. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 131 pci 6254 is a dual mode (transparent and non-transparent) universal pci-to-pci bridge. 19 non-transparent mode important: the pwrgd is not internally debounced . when in non-transparent mode, it must be debounced externally and a high input must reflect that the power is indeed stable. its asserting and deasserting edges can be asynchronous to p_clk and s_clk. 19.1 non-transparent m ode configuration space map pci 6254 can be configured to act as either a transparen t or non-transparent pci-to-pci bridge. the mode is selectable through the trans# pin. superscript legend: 1 = writable when read only register write enable bit is set 2 = eeprom loadable for part or all of the bits 7-0 3 = shared registers for primary and secondary ports 31-24 23-16 15-8 primary offset secondary offset 1,2,3 device id 1,2,3 vendor id 00h 40h primary status primary command 04h 44h 1,2,3 class code 3 revision id 08h 48h 1,2,3 bist 1,2,3 header type primary latency timer primary cache line size 0ch 4ch downstream i/o or memory 0 bar 10h 50h downstream memory 1 bar 14h 54h downstream memory 2 bar or downstream memory 1 bar upper 32 bits 18h 58h reserved 1ch ? 2bh 5ch-6bh 1,2,3 subsystem id 1,2,3 subsystem vendor id 2ch 6ch reserved 30h 70h reserved 3 capabilit y ptr 34h 74h reserved 38h 78h 1 primary maximum latency 1 primary minimum grant primary interrupt pin primary interrupt line 3ch 7ch 1,2,3 device id 1,2,3 vendor id 40h 00h secondary status secondary command 44h 04h 1,2,3 class code 3 revision id 48h 08h 1,2,3 bist 1,2,3 header type secondary latency timer secondary cache line size 4ch 0ch upstream i/o or memory 0 bar 50h 10h upstream memory 1 bar 54h 14h upstream memory 2 bar or upstream memory 1 bar upper 32 bits 58h 18h reserved 5ch ? 6bh 1ch-2bh pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 132 6ch 2ch 1,2,3 subsystem id 1,2,3 subsystem vendor id reserved 70h 30h reserved 3 capability ptr 74h 34h reserved 78h 38h 1 secondary maximum latency 1 secondary minimum grant secondary interrupt pin secondary interrupt line 7ch 3ch 19.1.1 configuration 80h-ffh, sh adow and extended registers important note: registers 80h-ffh, shadow registers and extended registers are shared registers and c an be accessed by both primary and secondary port. there should be extreme care in accessing such registers by both primary and secondary port masters. the use of the built-in semaphore mechanisms is recommended. 19.1.1.1 configuration 80h-ffh registers registers 80h-ffh, and the extended regi sters, are set to their default values upon power-up of the pci 6254. subsequent pci resets from p_rstin# and s_rstin# will not affect their values. xb downstream configuration address 80h 80h xb downstream configuration dataport 84h 84h xb upstream configuration address 88h 88h xb upstream configuration dataport 8ch 8ch reserved xb configuration access semphore status xb upstream configuration own semaphore xb downstream configuration own semaphore 90h 90h reserved serr# event disable clock control 94h 94h gpio[3:0] input data gpio{3:0] output enable control gpio{3:0] output data serr# status 98h 98h gpio[7-4] input register gpio[7-4] output enable gpio[7-4] output data hot swap switch ror control 9ch 9ch gpio[15-8] input register gpio[15-8] output enable gpio[15-8] output data pwrup status a0h a0h upstream message 3 upstream message 2 upstream message 1 upstream message 0 a4h a4h downstream message 3 downstream message 2 downstream message 1 downstream message 0 a8h a8h msi control next item ptr = 00 1,2,3 msi cap. id =5 (rev aa = 8) ach ach msi address b0h b0h msi upper address b4h b4h reserved msi data b8h b8h pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 133 reserved bch bch downstream doorbell request downstream doorbell enable c0h c0h upstream doorbell request upstream doorbell enable c4h c4h upstream interrupt enable downstream interrupt status downstream doorbell status c8h c8h downstream interrupt enable upstream interrupt status upstream doorbell status cch cch extended register index nt configuration own semaphore reserved reserved d0h d0h extended registers dataport d4h d4h arbiter control diagnostic control chip control d8h d8h 1,2 power management capabilities next item ptr = e4 capability id = 01 dch dch 1,2 power management data pmcsr bridge support 1,2 power management csr e0h e0h reserved hscsr = 00 next item ptr = e8 capability id = 06 e4h e4h vpd register = 0000 next item ptr = 00 capability id = 03 e8h e8h vpd data register = 0000_0000 ech ech reserved f0h-fch f0h-fch pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 134 19.1.1.2 extended register map 31-24 23-16 15-8 7-0 index 32 bit sticky register 0 0h 32 bit sticky register 1 1h 32 bit sticky register 2 2h 32 bit sticky register 3 3h 32 bit sticky register 4 4h 32 bit sticky register 5 5h 32 bit sticky register 6 6h 32 bit sticky register 7 7h 2 upstream bar 0 translation address 8h 2 upstream bar 1 translation address 9h 2 upstream bar 2 or upstream bar1 upper 32 bits translation address ah 2 upstream translation enable 2 upstream bar 2 translation mask 2 upstream bar 1 translation mask 2 upstream bar 0 translation mask bh 2 downstream bar 0 translation address ch 2 downstream bar 1 translation address dh 2 downstream bar 2 or downstream bar1 upper 32 bits translation address eh 2 downstream translation enable 2 downstream bar 2 translation mask 2 downstream bar 1 translation mask 2 downstream bar 0 translation mask fh pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 135 19.1.1.3 primary configuration shadow registers the following registers are normally shadowed and can only be accessed when chip control register d8h bit 6 is set to ?1?. these registers restored to their default value upon p_rstin# and s_rstin# and are accessible by both primary and secondary ports. 31-24 23-16 15-8 7-0 offset bridge control reserved 40h 2 misc options 2 timeout control 2 primary flow through control 44h 2 secondary incremental prefetch count 2 primar y incremental prefetch count 2 secondary prefetch line count 2 primary prefetch line count 48h reserved 2 secondary flow through control 2 secondary maximum prefetch count 2 primary maximum prefetch count 4ch reserved test register 2 internal arbiter control 50h eeprom data eeprom address eeprom control 54h reserved 58h-74h pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 136 19.2 non-transparent mode primar y configuration registers description except for the declared shared regist ers in the configuration space map above, primary and secondary ports have independent registers 0-3fh. non-transparent configuration space 80h-ffh are access ible by both primary and secondary masters. in order to avoid corruptions by the other master, pci 6254 implements an nt-configuration semaphore. it is recommended that any configuration write to the comm on space should use the semaphore implemented in register d2h. user must use the correct byte size when accessing the configuration regi sters in order to prevent unintended corruption of configuration registers. 19.2.1 pci standard configuration registers vendor id register (read only) ? offset 0h defaults to 3388(h). device id register (read only) ? offset 2h defaults to 0021(h) for non-transparent mode, 20h for transparent mode. (note: r/w - read/write, r/o - read only, r/w1c - read/ write 1 to clear) command register (read/write) ? offset 4h bit function type description 0 i/o space enable r/w controls the bridge?s response to i/o accesses on the primary interface. 0=ignore i/o transaction 1=enable response to i/o transaction reset to 0. 1 memory space enable r/w controls the bridge?s response to memory accesses on the primary interface. 0=ignore all memory transaction 1=enable response to memory transaction reset to 0. 2 bus master enable r/w controls the bridge?s ability to operate as a master on the primary interface. 0=do not initiate transaction on the primary interface and disable response to memory or i/o transactions on secondary interface 1=enable the bridge to operate as a master on the primary interface reset to 0. 3 special cycle enable r/o no special cycle implementation ( set to ?0? ). 4 memory write and invalidate enable r/o memory write and invalidate not supported ( set to ?0? ). pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 137 5 vga palette snoop enable r/w controls the bridge?s response to vga compatible palette accesses. 0=ignore vga palette accesses on the primary interface 1=enable response to vga palette writes on the primary interface (i/o address ad[9:0]=3c6h, 3c8h and 3c9h) reset to 0. 6 parity error enable r/w controls the bridge?s response to parity errors. 0=ignore any parity errors 1=normal parity checking performed reset to 0. 7 wait cycle control r/w pci 6254 performs address / data stepping (reset to ?1?). 8 p_serr# enable r/w controls the enable for the p_serr# pin. 0=disable the p_serr# driver 1=enable the p_serr# driver reset to 0. 9 fast back to back enable r/w controls the bridge?s ability to generate fast back-to-back transactions to different devices on the primary interface. 0=no fast back to back transaction 1=reserved. pci 6254 does not generate fast back to back transaction reset to 0. 10-15 reserved r/o reserved. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 138 status register(read/write) ? offset 6h bit function type description 0-3 reserved r/o reserved ( set to ?0?s ). 4 ecp r/o enhanced capabilities port. reads as 1 to indicate pci 6254 supports an enhanced capabilities list. 5 66mhz r/o reflects the state of cfg66 input pin. 1 = pci 6254 is 66mhz capable. 6 udf r/o no user-definable features ( set to ?0? ). 7 fast back to back capable r/o fast back-to-back write capable on primary side ( set to ?1? ). 8 data parity error detected r/wc it is set when the following conditions are met: 1. p_perr# is asserted 2. bit 6 of command register is set reset to 0. 9-10 devsel timing r/o devsel# timing. reads as 01b to indicate pci 6254 responds no slower than with medium timing 11 signaled target abort r/wc should be set (by a target devic e) whenever a target abort cycle occurs. reset to 0. 12 received target abort r/wc set to ?1? (by a master device) when transactions are terminated with target abort. reset to 0. 13 received master abort r/wc set to ?1? (by a master) when transactions are terminated with master abort. reset to 0. 14 signaled system error r/wc should be set whenever p_serr# is asserted. reset to 0. 15 detected parity error r/wc should be set whenever a parity er ror is detected regardless of the state of the bit 6 of command register. reset to 0. revision id register (read only) - offset 8h defaults to 04h. class code register (read only) ? offset 9h this register can be written to by enabling the ror write enable bit at register 9ch bit 7. defaults to 068000h for non-transparent mode, 060400 for transparent mode. cache line size register (read/write) ? offset 0ch this register is used when terminating memory writ e and invalidate transactions and when prefetching. only cache line sizes (in units of 32-bits words), which ar e power of two are valid (only one bit can be set in this register). reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 139 this register sets the value for master latency timer, which starts counting when the master asserts frame#. reset to 0. latency timer register (read/write) ? offset 0dh header type register (read only) ? offset 0eh defaults to 0 in non-transparent mode. bist register (read only) ? offset 0fh this register can be written to by enabling the ror write enable bit at register 9ch bit 7. reset to 0. i/o or memory bar 0 - offset 10h bit function type description 31:0 i/o or memory bar 0 r/w this base address register follows the standard pci base address register definition. its bar type and prefetchable area control is located in the corresponding bar control register located in the extended register. (for pci 6254 rev aa, when read, the i/o type indication bit 0 will only show 1 when i/o command is enabled in the command register at 04h bit 0 and the bar type is programmed to i/o.) memory bar 1 - offset 14h bit function type description 31:0 memory bar 1 r/w this base address register follows the standard pci base address register definition. its bar type and prefetchable area control is located in the corresponding bar control register located in the extended register. memory bar 2 - offset 18h bit function type description 31:0 memory bar 2 or memory bar1 upper 32 bits r/w this base address register follows the standard pci base address register definition. its bar type and prefetchable area control is located in the corresponding bar control register located in the extended register. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 140 19.2.2 subsystem vendor id and subsystem id the values reflected here are normally read on ly. however their default value can be changed by firmware or software by first tu rning the ror write enable bit at register 9ch bit 7. after any modifications to such registers, this write enable bit must be cleared to preserve their read only nature. subsystem vendor id (read only) - offset 2ch defaults to 3388h subsystem id (read only) - offset 2eh defaults to 0028h ecp pointer ? offset 34h(read/only) bit function type description 7-0 ecp pointer r/o enhanced capabilities port offset pointer. this register reads as dch to indicate the offset of the power management registers. interrupt line register (r/w) ? offset 3ch reset to 0. (for rev aa, secondary port interrupt line register ca n only be written to using word command, not byte command) interrupt pin register (read only) ? offset 3dh reads as 01 to indicate that pci 6254 uses interrupt pin. minimum grant register (read only) ? offset 3eh this register can be written to by enabling the ror write enable bit at register 9ch bit 7. reset to 0. maximum latency (read only) ? offset 3fh this register can be written to by enabling the ror write enable bit at register 9ch bit 7. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 141 19.2.3 secondary port standard pc i configuration re gisters shadow registers 40h-7fh reflect the imag e of the opposite port standard pc i configuration register 0h-3fh. upon transparent mode primary reset deass ertion or non-transparent mode powergood assertion, and during eeprom autoload phase, th e shadow registers are presented instead of the standard pci configuration image of the opposite port. however, the following shadow registers 42h-77h can be accessed by setting chip control register d8h bit 6 to ?1?. these are shared miscella neous control registers that are also used in transparent mode. bridge control register (read/write) ? offset 42h (reg 3eh in transparent mode) bit function type description 0 parity error response enable r/w controls the bridge?s response to parity errors on the secondary interface. 0=ignore address and data parity errors on the secondary interface 1=enable parity error reporting and detection on the secondary interface reset to 0. 1 s_serr# enable r/w controls the forwarding of s_ serr# to the primary interface. 0=disable the forwarding s_serr# to primary 1=enable the forwarding of s_serr# to primary reset to 0. 2 isa enable r/w controls the bridge?s resp onse to isa i/o addresses, which is limited to the first 64k. 0=forward all i/o addresses in the range defined by the i/o base and i/o limit registers 1=block forwarding of isa i/o addr esses in the range defined by the i/o base and i/o limit registers that are in the first 64k of i/o space that address the last 768 bytes in each 1kbytes block. secondary i/o transactions are forwarded upstream if the address falls within the last 768 bytes in each 1kbytes block reset to 0. 3 vga enable r/w controls the bridge?s response to vga compatible addresses. 0=do not forward vga compatible memory and i/o addresses from primary to secondary 1=forward vga compatible memory and i/o address from primary to secondary regardless of other settings reset to 0. 4 reserved r/o reserved (set to 0). 5 master abort mode r/w controls the bridge behavior in responding to master aborts on secondary interface 0=do not report master aborts (r eturn ffff_ffffh on reads and discards data on writes) 1=report master aborts by signaling target abort reset to 0. note: during lock cycles, pci 6254 ignores this bit, and always completes the cycle as a target abort. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 142 6 secondary reset r/w forces the assertion of sr st# signal pin on the secondary interface. 0=do not force the assertion of s_rstout# pin 1=force the assertion of s_rstout# pin reset to 0. 7 fast back to back enable r/w controls the bridge?s ability to generate fast back-to-back transactions to different devices on the secondary interface. 0=no fast back to back transaction 1=reserved. pci 6254 does not generate fast back to back cycle. reset to 0. 8 primary master timeout r/w sets the maximum number of pci clock for an initiator on the primary bus to repeat the delayed transaction request. 0=timeout after 2 15 pci clocks 1=timeout after 2 10 pci clocks reset to 0. 9 secondary master timeout r/w sets the maximum number of pci clock for an initiator on the secondary bus to repeat the delayed transaction request. 0=timeout after 2 15 pci clocks 1=timeout after 2 10 pci clocks reset to 0. 10 master timeout status r/wc set to ?1? when either primary master timeout or secondary master timeout. reset to 0. 11 master timeout p_serr# enable r/w enable p_serr# assertion during master timeout. 0=p_serr# not asserted on master timeout 1=p_serr# asserted on either primary or secondary master timeout. reset to 0. 12 master timeout s_serr# enable r/w enable s_serr# assertion during master timeout. 0=s_serr# not asserted on master timeout 1=s_serr# asserted on either primary or secondary master timeout. reset to 0. 13 p_serr# enable r/w controls the forwarding of p_se rr# to the secondary interface. 0=disable the forwarding p_serr# to secondary port 1=enable the forwarding of p_serr# to secondary port reset to 0. 15-14 reserved r/o reserved (set to ?0?s). pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 143 primary flow through control register - offset 44h bit function type description 2-0 primary posted write completion wait count r/w maximum number of clocks that pci 6254 will wait for posted write data from initiator if delivering write data in flow through mode and internal post write queues are almost empty. if the count is exceeded without any additional data from the initiator, the cycle to target will be terminated to be completed later. 000 : pci 6254 will terminate cycle if there is only 1 data entry left in the internal write queue. 001 : pci 6254 will deassert irdy#, and wait 1 clock for data before terminating cycle. ? 111 : pci 6254 will wait 7 clocks for source data. 3 reserved r/o reserved. returns 0 when read 6-4 primary delayed read completion wait count maximum number of clocks that pci 6254 will wait for delayed read data from target if returning read data in flow through mode and internal delayed read queue is almost full. if the count is exceeded without any additional space in the qu eue, the cycle to target will be terminated, and completed when initiato r retries the rest of the cycle. 000 : pci 6254 will terminate cycle if only 1 data entry is left in the read queue. 001 : pci 6254 will deassert trdy#, and wait 1 clock for data before terminating cycle. ? 111 : pci 6254 will wait 7 clocks for source data. 7 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 144 timeout control register - offset 45h bit function type description 2-0 maximum retry counter control r/w controls maximum number of times that pci 6254 will retry a cycle before signaling a timeout. this timeout applies to read/write retries and can be enabled to trigger serr# on the primary or secondary port depending the serr# ev ents that are enabled. maximum number of retries to timeout = 0000 : 2 24 0001 : 2 18 0010 : 2 12 0011 : 2 6 0111 : 2 0 reset to 0. 3 reserved r/o 5:4 primary master timeout divider r/w provides an additional option for the primary master timeout. timeout counter can optionally be divided by 256, in addition to its original setting in the bridge control register. original setting is 32k by default and programmable to 1k. 11 : timeout counter = primary master timeout / 256 10 : timeout counter = primary master timeout / 16 01 : timeout counter = primary master timeout / 8 00: counter = primary master timeout / 1 defaults to 0 7:6 secondary master timeout divider r/w provides an additional option for the secondary master timeout. timeout counter can optionally be divided by 256, in addition to its original setting in the bridge control register. original setting is 32k by default and programmable to 1k. 11 : timeout counter = primary master timeout / 256 10 : timeout counter = primary master timeout / 16 01 : timeout counter = primary master timeout / 8 00: counter = primary master timeout / 1 defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 145 miscellaneous options - offset 46h bit function type description 0 write completion wait for perr# r/w if 1, pci 6254 will always wait fo r perr# status of the target before completing a delayed write transaction to the initiator. defaults to 0 1 read completion wait for par r/w if 1, pci 6254 will always wait for par status of the target before completing a delayed read transaction to the initiator. defaults to 0 2 dtr out of order enable r/w if 1, pci 6254 may return delayed read transactions in a different order than requested. otherwise , delayed read transactions are returned in the same order as requested defaults to 0 3 generate parity enable r/w if 1, pci 6254 as a master will generate the par and par64 to cycles going across the bridge, otherwise, pci 6254 passes along the par/par64 of the cycle as stored in the internal buffers. defaults to 0 6-4 address step control r/w during configuration type 0 cy cles, pci 6254 will drive the address for the number of clocks specified in this register before asserting frame#. 000 : pci 6254 will assert frame# at the same time as the address. 001 : pci 6254 will assert frame# 1 clock after it drives the address on the bus. ? 111 : pci 6254 will assert frame# 7 clocks after it drives the address on the bus. 8-7 reserved 9 prefetch early termination r/w if 1, pci 6254 will terminate pref etching at the current calculated count if flowthrough is not yet achieved, and another prefetchable read cycle is accepted by the pci 6254. if 0, pci 6254 will always finish prefetching as programmed at the prefetch count registers, regardless of any other outstanding prefetchable reads in the transaction queue. 10 read minimum enable r/w if 1, pci 6254 will only initiate read cycles if there is available space in the fifo as specified by t he prefetch count registers. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 146 15,11 force 64 bit control r/w if set, 32-bit prefetchable reads or 32-bit posted memory write cycles on one side will be converted to 64- bit cycles on completion to target side if target supports 64-bit tran sfers. if set to 0, cycles are not converted. when combined with the control of bit 15 of this register, the following control is provided: (bit 15 is set to 0 for rev aa and cannot be changed) bit 15, 11 0, 0 disable (default) 0, 1 convert to 64 bit command onto both ports 1, 0 convert to 64 bit command onto secondary port 1, 1 convert to 64 bit command onto primary port starting address for all cycles using this feature should be on the qword boundary. defaults to 0 12 memory write and invalidate control r/w if 1, pci 6254 will pass memory write and invalidate commands if there is at least 1 cache line of fi fo space available, otherwise it will complete as a memory write cycle. if 0, pci 6254 will retry memory write and invalidate commands if there is no space for 1 cacheline of data in the internal queues. defaults to 0 13 primary lock enable r/w if 1, pci 6254 will follow the lock protocol on the primary interface. otherwise, lock is ignored. defaults to 1 14 secondary lock enable r/w if 1, pci 6254 will follow the lock protocol on the secondary interface. otherwise, lock is ignored. defaults to 0 15,11 force 64 bit control r/w see description in bit 11 section. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 147 bit 19.2.3.1 prefetch control registers registers 44h, 48h ? 4dh are the pref etch control registers, and are used to fine-tune memory read prefetch behavior of the pci 6254. detailed descriptions of thes e registers can be found in chapter 18 flow through optimization. primary initial prefetch count - offset 48h function type description 5-0 primary initial prefetch count r/w controls initial prefetch count on the primary bus during reads to prefetchable memory space. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. secondary initial prefetch count - offset 49h bit function type description 5-0 secondary initial prefetch count r/w controls initial prefetch count on the secondary bus during reads to prefetchable memory space. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. primary incremental prefetch count - offset 4ah bit function type description 5-0 primary incremental prefetch count r/w this controls incremental r ead prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge will prefetch an additional ?primary incremental prefetch count? dwords. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. this register value must not exceed half the value programmed in the primary maximum prefetch count register. otherwise, no incremental prefetch will be performed. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 148 secondary incremental prefetch count - offset 4bh bit function type description 5-0 secondary incremental prefetch count r/w this controls incremental r ead prefetch count. when an entry?s remaining prefetch dword count falls below this value, the bridge will prefetch an additional ?secondary incremental prefetch count? dwords. this register value should be a power of 2 (only one bit should be set to 1 at any time). value is number of double words. bit 0 is read only and is always 0. this register value must not exceed half the value programmed in the secondary maximum prefetch count register. otherwise, no incremental prefetch will be performed. defaults to 10h. 7-6 reserved r/o reserved. returns 0 when read. primary maximum prefetch count - offset 4ch bit function type description 5-0 primary maximum prefetch count r/w this value limits the cumulative maximum count of prefetchable dwords that are allocated to one entry on the primary when flow through for that entry was not achieved. this register value should be an even number. bit 0 is read only and is always 0. exception: 0h = 256 bytes = maximum programmable count defaults to 20h. 7-6 reserved r/o reserved. returns 0 when read. secondary maximum prefetch count - offset 4dh bit function type description 5-0 secondary maximum prefetch count r/w register limits the cumulative maximum count of prefetchable dwords that are allocated to one entry on the secondary when flow through for that entry was not achieved. this register value should be an even number. bit 0 is read only and is always 0. exception: 0h = 256 bytes = maximum programmable count defaults to 20h. 7-6 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 149 secondary flow through control register - offset 4eh bit function type description 2-0 secondary posted write completion wait count r/w 001 : pci 6254 will deassert irdy#, and wait 1 clock for data before terminating cycle. maximum number of clocks that pci 6254 will wait for posted write data from initiator if delivering write data in flow through mode and internal post write queues are al most empty. if the count is exceeded without any additional data from the initiator, the cycle to target will be terminated, to be completed later. 000 : pci 6254 will terminate cycle if there is only 1 data entry left in the internal write queue. ? 111 : pci 6254 will wait 7 clocks for source data. 3 reserved r/o reserved. returns 0 when read 6-4 secondary delayed read completion wait count maximum number of clocks that pci 6254 will wait for delayed read data from target if returning read data in flow through mode and internal delayed read queue is almost full. if the count is exceeded without any additional space in the qu eue, the cycle to target will be terminated, and completed when initiato r retries the rest of the cycle. ? 000 : pci 6254 will terminate cycle if only 1 data entry is left in the read queue. 001 : pci 6254 will deassert trdy#, and wait 1 clock for data before terminating cycle. 111 : pci 6254 will wait 7 clocks for source data. 7 reserved r/o reserved. returns 0 when read. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 150 internal arbiter control register - offset 50h bit function type description 0 low priority group fixed arbitration r/w if 1, the low priority group uses the fixed priority arbitration scheme, otherwise a rotating priority arbitration scheme is used defaults to 0 1 low priority group arbitration order r/w this bit is only valid when the low priority arbitration group is set to a fixed arbitration scheme. if 1, priority decreases in ascending numbers of the master, for example master #4 will have higher priority than master #3. if 0, the reve rse is true. this order is relative to the master with the highest priority for this group, as specified in bits 7-4 of this register. defaults to 0 2 high priority group fixed arbitration r/w if 1, the high priority group uses the fixed priority arbitration scheme, otherwise a rotating priority arbitration scheme is used defaults to 0 3 high priority group arbitration order r/w this bit is only valid when the high priority arbitration group is set to a fixed arbitration scheme. if 1, priority decreases in ascending numbers of the master, for example master #4 will have higher priority than master #3. if 0, the reve rse is true. this order is relative to the master with the highest priority for this group, as specified in bits 11-8 of this register. defaults to 0 7-4 highest priority master in low priority group r/w controls which master in the low priority group has the highest priority. it is valid only if the gr oup uses the fixed arbitration scheme. 0000 : master#0 has highest priority 0001 : ? 1001 : pci 6254 has highest priority 1010-1111 : reserved defaults to 0 11-8 highest priority master in high priority group r/w controls which master in the high priority group has the highest priority. it is valid only if the gr oup uses the fixed arbitration scheme. 0000 : master#0 has highest priority 0001 : ? 1001 : pci 6254 has highest priority 1010-1111 : reserved defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 151 0000 : last master granted is parked 12-15 bus parking control r/w controls bus grant behavior during idle. 0001 : master #0 is parked ? 1001 : master #8 is parked 1010 : pci 6254 is parked other : grant is deasserted defaults to 0 pci 6254 test register ? offset 52h bit function type description 0 eeprom autoload control r/w if 1, disables eeprom autoload. this is a testing feature only. in order to stop eeprom load in transparent mode, 1 must be written into this register within 1200 clocks after p_rstin# goes high. in non-transparent mode, 1 must be written into this register within 1200 clocks after pwrgd goes high. 1 fast eeprom autoload r/w if 1, speeds up eeprom autoload by 32 times. this is a testing feature only. in order to enable fast eeprom load in transparent mode, 1 must be written into this register within 1200 clocks after p_rstin# goes high. in non- transparent mode, 1 must be written into this register within 1200 clocks after pwrgd goes high. 2 eeprom autoload status r/o status of eeprom autoload. 3 reserved r/o reserved 4 64en# r/o reflects the 64en# pin status 5 s_cfn# r/o reflects the s_cfn# pin status 6 trans# r/o reflects the trans# pin status 7 u_mode r/o reflects the u_mode pin status pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 152 eeprom control - offset 54h bit function type description 0 start r/w starts the eeprom read or write cycle. 1 eeprom command r/w controls the command sent to the eeprom 1 : write 0 : read 2 eeprom error r/o this bit is set to 1 if eepr om ack was not received during eeprom cycle. 3 eeprom autoload successful r/o this bit is set to 1 if eeprom autoload occurred su ccessfully after reset, and some configuration regi sters were loaded with values programmed in the eeprom. if zero, eeprom autoload was unsuccessful or was disabled. 5-4 reserved r/o reserved. returns ?0? when read. 7-6 eeprom clock rate r/w controls frequency of eeprom clock. eeprom clock is derived from the primary pci clock. 00 = pclk/1024 (used for 66mhz pci) 01 = pclk/512 10 = pclk/256 11 = pclk/32 (for test mode use) defaults to 00 eeprom address - offset 55h type bit function description 0 reserved r/o starts the eeprom read or write cycle. 7-1 eeprom address r/w word address for eeprom cycle. eeprom control - offset 56h bit function type description 15-0 eeprom data r/w contains data to be written to the eeprom. during reads, this register contains data received fr om the eeprom after a read cycle has completed. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 153 19.2.4 cross bridge configurat ion access control registers registers 80h-87h, 90h cannot be written from downst ream side while 88h-8fh, 91h cannot be written from upstream side. configuration address should al ways be first setup before access should be made to the configuration dataport. xb downstream configuration address - offset 80h bit function type description 31:0 downstream configuration address r/w the data in this register is used as the downstream configuration address. default = 0h xb downstream configuration dataport - offset 84h bit function type description 31:0 downstream configuration dataport r/w the data presented at this register is used as the downstream configuration read/write data. default = 0h xb upstream configuration address - offset 88h bit function type description 31:0 upstream configuration address r/w the data in this register is used as the upstream configuration address. default = 0h xb upstream configuration dataport - offset 8ch bit function type description 31:0 upstream configuration dataport r/w the data presented at this r egister is used as the upstream configuration read/write data. default = 0h xb downstream configuration ownership semaphore register ? offset 90h bit function type description 0 downstream configurations own r/w1c only upstream master can acce ss this register using byte width access. when read as ?0? by upstream interface with intention to access downstream configuration registers, it indicates that downstream configuration address and data registers are not owned and can be accessed. the read operation will automatically set this bit to ?1? to indicated it will be owned. the owner should issue a configuration write ?1? to clear this register after use. software can check this semaphore status via register 92h bit 0 without taking ownership. 7:1 reserved ro pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 154 bit xb upstream configuration ownership semaphore register ? offset 91h function type description 0 upstream configurations own r/w1c only downstream master can access this register using byte width access. when read as ?0? by downstream interface with intention to access upstream configuration registers, it indicates that upstream configuration address and data registers are not owned and can be accessed. the read operation will automatically set this bit to ?1? to indicated it will be owned. the owner should issue a configuration write ?1? to clear this register after use. software can check this semaphore status via register 92h bit 1 without taking ownership. 7:1 reserved ro xb configuration ownership status register (read only) ? offset 92h bit function type description 0 downstream configurations own bit ro allows the examination of do wnstream configuration own bit without setting it. 1 upstream configurations own bit ro allows the examination of upst ream configuration own bit without setting it. 7:2 reserved ro clock control register (read/write) ? offset 94h bit function type description 1:0 clock 0 disable r/w if either bit is 0, s_clkout[0] is enabled. when both bits are 1, s_clkout[0] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 0. 3:2 clock 1 disable r/w if either bit is 0, s_clko[1] is enabled. when both bits are 1, s_clko[1] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 1. 5:4 clock 2 disable r/w if either bit is 0, s_clko[2] is enabled. when both bits are 1, s_clko[2] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 2. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 155 7:6 clock 3 disable r/w if either bit is 0, s_clko[3] is enabled. when both bits are 1, s_clko[3] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. these bits are assigned to correspond to the prsnt# pins for slot 3. 8 clock 4 disable r/w if 0, s_clko[4] is enabled. when 1, s_clko[4] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 9 clock 5 disable r/w if 0, s_clko[5] is enabled. when 1, s_clko[5] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 10 clock 6 disable r/w if 0, s_clko[6] is enabled. when 1, s_clko[6] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 11 clock 7 disable r/w if 0, s_clko[7] is enabled. when 1, s_clko[7] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 12 clock 8 disable r/w if 0, s_clko[8] is enabled. when 1, s_clko[8] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 13 clock 9 disable r/w if 0, s_clko[9] is enabled. when 1, s_clko[9] is disabled. upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 15-14 reserved r/o reserved pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 156 serr# event disable register - offset 96h if p_boot = 1, s_serr# is driven when the following events occur. if p_boot = 0, p_serr# is driven. bit function type description 0 address parity error r/w1 c signal serr# was asserted due to address parity error on either side of the bridge. reset to 0. 1 posted write parity error r/w controls ability of pci 6254 to assert p_serr# when a data parity error is detected on the target bus during a posted write transaction. serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 2 posted memory write nondelivery r/w controls ability of pci 6254 to assert serr# when it is unable to deliver posted write data after 2 24 (or programmed maximum retry count at timeout control register) attempts. serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 3 target abort during posted write r/w controls ability of pci 6254 to assert serr# when it receives a target abort when attempting to de liver posted write data. serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 4 master abort on posted write r/w controls ability of pci 6254 to assert serr# when it receives a master abort when attempting to deliver posted write data. serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 5 delayed configuration or io write nondelivery r/w controls ability of pci 6254 to assert serr# when it is unable to deliver delayed write data after 2 24 (or programmed maximum retry count at timeout control register) attempts. serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 6 delayed read- no data from target r/w controls ability of pci 6254 to assert serr# when it is unable to transfer any read data from the target after 2 24 (or programmed maximum retry count at timeout control register) attempts. serr# is asserted if this event occurs when this bit is 0 and serr# enable bit in the command register is set. reset value is 0. 7 posted write data parity error r/w1 c signal serr# was asserted due to a posted write data parity error on the target bus. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 157 serr# status register (read/write) ? offset 98h bit function type description 0 primary post write nondelivery r/w1c signal p_serr# was asserted because pci 6254 was unable to deliver posted write data to t he target before timeout counter expires. reset to 0. 1 primary delayed write nondelivery r/w1c signal p_serr# was asserted because pci 6254 was unable to deliver delayed write data before time -out counter expires. reset to 0. 2 primary delayed read failed r/w1c signal p_serr# was asserted because pci 6254 was unable to read any data from the target be fore time-out counter expires. reset to 0. 3 primary delayed transaction master timeout r/w1c signal p_serr# was asserted because a master did not repeat a read or write transaction before the master timeout counter expired on the initiator?s bus. reset to 0. 4 secondary post write nondelivery r/w1c signal s_serr# was asserted because pci 6254 was unable to deliver posted write data to t he target before timeout counter expires. reset to 0. 5 signal s_serr# was asserted because pci 6254 was unable to deliver delayed write data before time -out counter expires. reset to 0. secondary delayed write nondelivery r/w1c 6 secondary delayed read failed r/w1c signal s_serr# was asserted because pci 6254 was unable to read any data from the target be fore time-out counter expires. reset to 0. 7 secondary delayed transaction master timeout r/w1c signal s_serr# was asserted because a master did not repeat a read or write transaction before the master timeout counter expired on the initiator?s bus. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 158 19.2.5 gpio registers description gpio[3:0] output data register - offset 99h bit function type 3:0 gpio[3:0] output write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit low on the gpio[3:0] bus if it is programmed as output. writing 0 has no effect. read returns the last written value. resets to 0. 7:4 gpio[3:0] output write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit high on the gpio[3:0] bus if it is programmed as output. writing 0 has no effect. read returns the last written value. resets to 0. gpio[3:0] output enable register - offset 9ah bit function type description 3:0 gpio output enable write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[3:0] bus as input only. writing 0 has no effect. read returns the last value written. resets to 0. 7:4 gpio output enable write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[3:0] bus as output. gpio[3:0] then drives the value set in the output data register (reg 99h). writing 0 has no effect. read returns the last written value. resets to 0. gpio[3:0] input data register - offset 9bh bit function type description 3:0 reserved r/o reserved 7:4 gpio[3:0] input data r/o this read-only register reads t he state of the gpio[3:0] pins. the state is updated on the pci clock cycle following a change in the gpio[3:0] state. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 159 hot swap switch and ror register control (r/w) ? offset 9ch bit function type description 0 hot swap extraction switch r/w hot swap extraction switch : software switch used to signal extraction of board. if set, board is in in serted state. writing a ?0? to this bit will signal the pending extraction of the board. 6-1 reserved r/o reserved 7 ror write enable r/w read only registers write enable: subsystem vender id at register 2ch and subsystem id register at 2eh are normally read only. setting this bit to 1 will enable write to such read only id registers. power management regist ers deh, e0h, and e 3h are normally read only. setting this bit to 1 will enabl e write to all read only power management registers. this bit must be cleared after the desired values have been modified in the read only registers. gpio[7:4] output data register - offset 9dh bit function type description 3:0 gpio[7:4] output write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit low on the gpio[7:4] bus if it is programmed as output. writing 0 has no effect. defaults to 0 7:4 gpio[7:4] output write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit high on the gpio[7:4] bus if it is programmed as output. writing 0 has no effect gpio[7:4] output enable register - offset 9eh bit function type description 3:0 gpio[7:4] output enable write 1 to clear r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[7:4] bus as input only. writing 0 has no effect, reads returns last value written. defaults to 0 7:4 gpio[7:4] output enable write 1 to set r/w1 tc writing 1 to any of these bits drives the corresponding bit on the gpio[7:4] bus as output. gpio[7:4] then drives the value set in the output data register (reg 65h). writing 0 has no effect, reads returns last value written. defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 160 gpio[7:4] input data register - offset 9fh bit function type description 3:0 reserved r/o reserved 7:4 gpio[7:4] input data r/o this read-only register reads t he state of the gpio[7:4] pins. the state is updated on the pci clock cycle following a change in the gpio[7:4] state. power up status register - offset a0h bit function type description 7-0 power up status r/o power up latched status bits: upon pwrgd (power good), the status of gpio[15:8] are latched in this registers. user can choose to use such status for any desired option setting or checking. some recommended use (must be 3.3v input): gpio15: primary power state: 1 = primary port power is stable. gpio14: secondary power state: 1 = secondary port power is stable. gpio [15:8] output data register - offset a1h bit function type description 7:0 gpio[15:8] output data r/w gpio[15:8] output data. defaults to 0 gpio [15:8] output enable register - offset a2h bit function type description 7:0 gpio[15:8] output enable r/w writing 1 to any of these bits drives the corresponding bit on the gpio[15:8] bus as output. defaults to 0 gpio[15:8] input data register - offset a3h bit function type description 7:0 gpio[15:8] input data r/o this read-only register reads t he state of the gpio[15:8] pins. the state is updated on the pci clock cycle following a change in the gpio[15:8] state. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 161 19.2.6 direct message interrupt registers when enabled, a write command to the following message registers can cause a pci interrupt. the direct message interrupt registers allow faster than doorbell regi ster responds with the encoded interrupt message available. s_inta# will be ac tivated by downstream messages while p_inta# will be activated by upstream messages. upstream message 0 register - offset a4h bit function type description 7:0 upstream 0 register r/w secondary port masters can write data to this register for primary port devices to read. reading this register clears the secondary message interrupt status bit. upstream message 1 register - offset a5h bit function type description 15:8 upstream message 1 register r/w secondary port masters can write data to this register for primary port devices to read. reading this register clears the secondary message interrupt status bit. upstream message 2 register - offset a6h bit function type description 23:16 upstream message 2 register r/w secondary port masters can write data to this register for primary port devices to read. reading this register clears the secondary message interrupt status bit. upstream message 3 register - offset a7h bit function type description 31:24 upstream message 3 register r/w secondary port masters can write data to this register for primary port devices to read. reading this register clears the secondary message interrupt status bit. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 162 downstream message 0 register - offset a8h bit function type description 7:0 downstream message 0 register r/w primary port masters can write dat a to this register for secondary port devices to read. reading this register clears the secondary message interrupt status bit. downstream message 1 register - offset a9h bit function type description 15:8 downstream message 1 register r/w primary port masters can write dat a to this register for secondary port devices to read. reading this register clears the secondary message interrupt status bit. downstream message 2 register - offset aah bit function type description 23:16 downstream message 2 register r/w primary port masters can write dat a to this register for secondary port devices to read. reading this register clears the secondary message interrupt status bit. downstream message 3 register - offset abh bit function type description 31:24 downstream message 3 register r/w primary port masters can write dat a to this register for secondary port devices to read. reading this register clears the secondary message interrupt status bit. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 163 set to 00h. it indicates the end of the capabilities list. 19.2.7 message signal interrupt registers msi capability identifier (r/o) - offset ach this register is set to 08h. this register identifies this item in the capabilities list as an msi register set. next item pointer (r/o) - offset adh msi control - offset aeh this register provides syst em software control over msi. bit function type description 0 msi enable r/w system configuration software sets this bit to enable msi. 3-1 multiple message capable r/o system software reads this field to determine the number of requested messages. 6-4 multiple message enable r/w system software wr ites to this field to indicate the number of allocated messages. 7 64-bit address capable r/o system configuration software reads this bit. 15-8 reserved r/o reserved. reset to 0 msi address - offset b0h this register provides syst em software control over msi. bit function type description 1-0 reserved r/o reserved. reset to 0. 31-2 message address r/w system-specified message address. msi upper address - offset b4h this register provides syst em software control over msi. bit function type description 31-0 message upper address r/w system-specified message upper address. msi data - offset b8h this register provides syst em software control over msi. bit function type description 15-0 message data r/w system-specified message. each msi function is allocated up to 32 unique messages. 31-16 reserved r/o reserved. reset to 0. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 164 19.2.8 doorbell and miscellane ous interrupt registers when there are active downstream interrupt sources, s_inta# will be activated. when there are active upstream interrupt sources, p_inta# will be activated. downstream doorbell interrupt enable - offset c0h bit function type description 15:0 secondary interrupt requests enable r/w request to secondary port - software interrupt requests enable. downstream doorbell interrupt requests - offset c2h bit function type description 15:0 doorbell interrupts r/w primary mast ers setting these bits to 1 will cause interrupts on the secondary port. as long as this bit is 1, the corresponding interr upt status bit cannot be cleared and new interrupts will be caused. therefore this bit should be cleared immediately after it has been set to generate an interrupt. upstream doorbell interrupt enable - offset c4h bit function type description 15:0 primary interrupt requests enable r/w request to primary port - software interrupt requests enable. upstream doorbell interrupt requests - offset c6h bit function type description 15:0 doorbell interrupts r/w secondary mast ers setting these bits to 1 will cause interrupts on the primary port. as long as this bit is 1, the corresponding interrupt status bit cannot be cleared and new interrupts will be caused. therefore this bit should be cleared immediately after it has been set to generate an interrupt. downstream doorbell interrupt status - offset c8h bit function type description 15:0 secondary interrupt requests r/w1c any set bit indicates the corresponding secondary software interrupt request to the secondary host is detected. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 165 bit downstream interrupt status - offset cah function type description 0 downstream message 0 r/w1c primary to secondary message 0 has been written. 1 downstream message 1 r/w1c primary to secondary message 1 has been written. 2 downstream message 2 r/w1c primary to secondary message 2 has been written. 3 downstream message 3 r/w1c primary to secondary message 3 has been written. 4 p_rstin# deassertion r/w1c deas sertion of p_rstin# detected. 5 p_pme# deassertion r/w1c deassertion of p_pme# detected. 6 gpio15 active low interrupt recommended use: primary power is not available ro this reflects the inverted state of the gpio15 pin if this interrupt is enabled. otherwise it is always 0. (rev aa: this feature is not available) 7 gpio5 active low interrupt ro this reflec ts the inverted state of the gpio5 pin if this interrupt is enabled. otherwise it is always 0. (rev aa: this feature is not available) upstream interrupt enable - offset cbh bit function type description 0 secondary to primary message 0 event interrupt trigger enable. upstream message 0 interrupt enable r/w 1 upstream message 1 interrupt enable r/w secondary to primary message 1 event interrupt trigger enable. 2 upstream message 2 interrupt enable r/w secondary to primary message 2 event interrupt trigger enable. 3 upstream message 3 interrupt enable r/w secondary to primary message 3 event interrupt trigger enable. 4 s_rstin# deassertion enable r/w deassertion of s_rstin# detection enable. 5 s_pme# deassertion enable r/w deassertion of s_pme# detection enable. 6 secondary external interrupt at gpio14 pin r/w gpio14 pin low triggers interrupt enable (rev aa: this feature is not available) 7 secondary external interrupt at gpio4 pin r/w gpio4 pin low triggers interrupt enable (rev aa: this feature is not available) upstream doorbell interrupt status - offset cch bit function type description 15:0 primary interrupt requests r/w1c any set bit indicates the corresponding primary interrupt request to the primary host is detected. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 166 upstream interrupt status - offset ceh bit function type description 0 upstream message 0 r/w1c secondary to primary message 0 has been written. 1 upstream message 1 r/w1c secondary to primary message 1 has been written. 2 upstream message 2 r/w1c secondary to primary message 2 has been written. 3 upstream message 3 r/w1c secondary to primary message 3 has been written. 4 s_rstin# deassertion r/w1c deas sertion of s_rstin# detected. 5 s_pme# deassertion r/w1c deassertion of s_pme# detected. 6 gpio14 active low interrupt recommended use: secondary power is not available ro this reflects the inverted state of the gpio14 pin if this interrupt is enabled. otherwise it is always 0. (rev aa: this feature is not available) 7 gpio4 active low interrupt ro this reflec ts the inverted state of the gpio4 pin if this interrupt is enabled. otherwise it is always 0. (rev aa: this feature is not available) downstream interrupt enable - offset cfh bit function type description 0 downstream message 0 interrupt enable r/w primary to secondary message 0 event interrupt trigger enable. 1 downstream message 1 interrupt enable r/w primary to secondary message 1 event interrupt trigger enable. 2 downstream message 2 interrupt enable r/w primary to secondary message 2 event interrupt trigger enable. 3 downstream message 3 interrupt enable r/w primary to secondary message 3 event interrupt trigger enable. 4 p_rstin# deassertion enable r/w deassertion of p_rstin# detection enable. 5 p_pme# deassertion enable r/w deassertion of p_pme# detection enable. 6 primary external interrupt at gpio15 pin r/w gpio15 pin low triggers interrupt enable (rev aa: this feature is not available) 7 primary external interrupt at gpio5 pin r/w gpio5 pin low triggers interrupt enable (rev aa: this feature is not available) pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 167 nt configuration own semaphore - offset d2h bit function type description 0 nt configuration own semaphore r/w1c when either primary or secondary port does a configuration read to this semaphore bit, it returns ?0? if there is no configuration read beforehand. such a read will then cause this semaphore bit to become ?1? automatically. any further read by other primary or secondary masters will see a ?1? (already owned). this bit must be cleared by the owner master using a configuration write ?1? to this register. software can check this semaphore status via register d8h bit 0 without taking ownership. 7:1 reserved ro reserved pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 168 19.2.9 extended registers there are eight 32bit sticky scratc h registers available in pci 6254 and they are at extended address 0h-7h. address translation registers are also located in the extended register area. extended register index - offset d3h bit function type description 7:0 extended index address r/w index address for extended registers extended register dataport - offset d4h bit function type description 31:0 extended registers dataport r/w a configuration write will cause the data presented at this port to be written into the register addressed by the extended register index. a configuration read will cause the data from the register addressed by the extended register index to be presented to this port. extended registers register index 32 bit sticky register 0 0h 32 bit sticky register 1 1h 32 bit sticky register 2 2h 32 bit sticky register 3 3h 32 bit sticky register 4 4h 32 bit sticky register 5 5h 32 bit sticky register 6 6h 32 bit sticky register 7 7h upstream bar 0 translation address 8h upstream bar 1 translation address 9h upstream bar 2 translation address ah upstream translation enable upstream bar 2 translation mask upstream bar 1 translation mask upstream bar 0 translation mask bh downstream bar 0 translation address ch downstream bar 1 translation address dh downstream bar 2 translation address eh downstream translation enable downstream bar 2 translation mask downstream bar 1 translation mask downstream bar 0 translation mask fh pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 169 32 bit sticky scratch registers - extended register index 0h-7h bit function type description 31:0 scratch register r/w sticky scratch register. upon power good, their values are undefined. if power is good, p_rstin# and s_rstin# active inputs do not affect their pre-existing value. type 19.2.9.1 address translation control registers upstream bar 0 translation address - extended register index 8h bit function description 31:0 upstream bar 0 translation address r/w bar 0 translation address. bits 11:0 are read only and always 0. only address a31:a12 are translated. lower address bits will be passed. upstream bar 1 translation address - extended register index 9h bit function type description 31:0 upstream bar 1 translation address r/w bar 1 translation address. bits 19:0 are read only and always 0. only address a31:a20 are translated. lower address bits will be passed. upstream bar 2 translation address - extended register index ah type bit function description 31:0 upstream bar 2 translation address r/w bar 2 translation address. bits 19:0 are read only and always 0. only address a31:a12 are translated. lower address bits will be passed. if bar1 is configured as 64bit bar, then this register contains the upper 32 bits of the bar1 translation address. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 170 upstream bar control - offset bh bit function type description upstream bar 0 translation mask 4:0 msb position of address mask r/w number of local address bits for bar 0 mask. default = 1fh (bar disabled) this value must be at least 2 to indicate the masking of a3-a0 and must not exceed the value 1eh to indicate the masking of a30-a0. 5 reserved r/o reserved 6 bar type r/w if 1, bar 0 points to i/o space, else memory defaults to 0 (for pci 6254 rev aa, when prog rammed to 1, io space must also be enabled in the pci command register at 4h bit 0.) 7 prefetchable r/w if 1, area pointed to by bar 0 is in prefet chable area, else area is non-prefetchable. defaults to 0 upstream bar 1 translation mask 13:8 msb position of address mask r/w number of local address bits for bar 1 mask. default = 3fh (bar disabled) this value must be at least 2 to indicate the masking of a3-a0 and must not exceed the value 3eh to indicate the masking of a62-a0. 14 bar type r/w if 0, bar 1 is only a 32- bit bar. otherwise, bar1 is a 64-bit bar. defaults to 0 15 prefetchable r/w if 1, area point ed to by bar 1 is in prefet chable area, else area is non-prefetchable. defaults to 0 upstream bar 2 translation mask 20:16 msb position of address mask r/w number of local address bits for bar 2 mask. default = 1fh (bar disabled) this value must be at least 2 to indicate the masking of a3-a0 and must not exceed the value 1eh to indicate the masking of a30-a0. 22:21 reserved r/o reserved 23 prefetchable r/w if 1, area point ed to by bar 2 is in prefet chable area, else area is non-prefetchable. defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 171 upstream translation enable 24 upstream bar 0 enable r/w if 1, address translation using bar 0 is enabled defaults to 0 25 upstream bar 1 enable r/w if 1, address translation using bar 1 is enabled defaults to 0 26 upstream bar 2 enable r/w if 1, address translation using bar 2 is enabled defaults to 0 30:27 reserved r/o reserved 31 s_port ready r/w upon s_rstin#, this bit is cleared. this bit should be set by secondary port master upon completion of secondary port initialization. when p_boot = 0 (secondary port has boot priority), primary port master access to pci standard bar configurations at 10h-1bh will be retried until s_portready bit is set. when p_boot = 0 and when this bit is ?0?, all cross bridge traffic initiated by primary port will be returned with retry. the port_ready mechanism does not have the above effect if the special fixed size cross bridge communication window is enabled when the xb_mem input is ?1?. downstream bar 0 translation address - extended register index ch bit function type description 31:0 downstream bar 0 translation address r/w bar 0 translation address. bits 11:0 are read only and always 0. only address a31:a12 are translated. lower address bits will be passed. downstream bar 1 translation address - extended register index dh bit function type description 31:0 downstream bar 0 translation address r/w bar 1 translation address. bits 19:0 are read only and always 0. only address a31:a20 are translated. lower address bits will be passed. downstream bar 2 translation address - extended register index eh bit function type description 31:0 downstream bar 0 translation address r/w bar 2 translation address. bits 11:0 are read only and always 0. only address a31:a12 are translated. lower address bits will be passed. if bar1 is configured as 64bit bar, then this register contains the upper 32 bits of the bar1 translation address. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 172 downstream bar control - offset fh bit function type description downstream bar 0 translation mask 4:0 msb position of address mask r/w number of local address bits for bar 0 mask. default = 1fh (bar disabled) this value must be at least 2 to indicate the masking of a3-a0 and must not exceed the value 1eh to indicate the masking of a30-a0. 5 reserved r/o reserved 6 bar type r/w if 1, bar 0 points to i/o space, else memory defaults to 0 (for pci 6254 rev aa, when prog rammed to 1, io space must also be enabled in the pci command register at 4h bit 0.) 7 prefetchable r/w if 1, area pointed to by bar 0 is in prefet chable area, else area is non-prefetchable. defaults to 0 downstream bar 1 translation mask 13:8 msb position of address mask r/w number of local address bits for bar 1 mask. default = 3fh (bar disabled) this value must be at least 2 to indicate the masking of a3-a0 and must not exceed the value 3eh to indicate the masking of a62-a0. 14 bar type r/w if 0, bar 1 is only a 32-bi t bar 1. otherwise, bar1 is a 64-bit bar. defaults to 0 15 prefetchable r/w if 1, area pointed to by bar 1 is in prefetchable area, else area is non-prefetchable. defaults to 0 downstream bar 2 translation mask 20:16 msb position of address mask r/w number of local address bits for bar 2 mask. default = 1fh (bar disabled) this value must be at least 2 to indicate the masking of a3-a0 and must not exceed the value 1eh to indicate the masking of a30-a0. 22:21 reserved r/o reserved 23 prefetchable r/w if 1, area point ed to by bar 2 is in prefet chable area, else area is non-prefetchable. defaults to 0 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 173 downstream translation enable 24 downstream bar 0 enable r/w if 1, address translation using bar 0 is enabled defaults to 0 25 downstream bar 1 enable r/w if 1, address translation using bar 1 is enabled defaults to 0 26 downstream bar 2 enable r/w if 1, address translation using bar 2 is enabled defaults to 0 30:27 reserved r/o reserved 31 p_port ready r/w upon p_rstin#, this bit is cleared. this bit should be set by primary port master upon completion of primary port initialization. when p_boot = 1 (primary port has boot priority), secondary port master access to pci standard bar configurations at 10h-1bh will be retried until p_portready bit is set. when p_boot = 1 and when this bit is ?0?, all cross bridge traffic initiated by secondary port will be returned with retry. the port_ready mechanism does not have the above effect if the special fixed size cross bridge communication window is enabled when the xb_mem input is ?1?. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 174 19.2.10 general control registers chip control register (read/write) ? offset d8h bit function type description 0 nt configuration semaphore status r/o this is the nt-configuration semaphore bit status. software can check the semaphore status via this bit without taking ownership. 1 memory write disconnect control r/w controls when the chip as a target disconnects memory transactions. when 0, disconnects on queue full or on a 4kb boundary. when 1, disconnects on a cache line boundary, as well as when the queue fills or on a 4 kb boundary. reset value is 0. 2 private or cross bridge memory enable r/w (transparent mode) 1 = enable private memory block reserved only for secondary memory space. the memory space can be programmed using the private memory base/limit registers. if limit is smaller than base, the private memory space is disabled. primary port cannot access this memory space through the bridge and the secondary port will not respond to any memory cycles addressing this private memory space. (in addition in rev aa, the cross-bridge memory window, default at 0-16m space and programmable later by software, is also treated as a private memory block in transparent mode.) (non-transparent mode) cross-bridge memory window enable: when this bit is ?1?, pci 6254 will automatically claim 16m of memory space. this allows the boot up of the low priority boot port to move forward without waiting for the priority boot port to program the corresponding memory bar registers. if this bit is ?1?, the primary or secondary port_ready mechanism will not be relevant and access to bar regi sters will not be retried. although the default claims 16m, the bar registers can be changed by eeprom or software to change the window size. in both transparent and non-transparent modes, this bit resets to the value as presented at the xb_mem input pin. after reset, this bit can be reprogrammed. 3 reserved r/o 4 secondary bus prefetch disable r/w controls pci 6254?s ability to pref etch during upstream memory read transactions. when written 0 the chip prefetches and does not forward byte enable bits during memory read transactions. when written 1, pci 6254 requests only one dword from the target during memory read transactions and forwards read enable bits. pci 6254 returns a target disconnect to the requesting master on the first data transfer. memory read line and memory read multiple transactions are still prefetchable. reset to 0 in the register. important: the read value of this bit is the inverted value of the actual register value. therefore upon reset, the read value is 1. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 175 5 live insertion mode r/w enables hardware control of transaction forwarding in the pci 6254. when 0, pin gpio[3] has no effect on the i/o, memory, and master enable bits. when 1, if gpio[3] is set as input, and gpio[3] is driven high, i/o, memory and master enable bits are disabled. 6 transparent access r/w enables the access to shadow registers which are also transparent mode registers 44h-5fh under non-transparent mode. this defaults to ?0?. 7 reserved r/o reserved (set to 0) diagnostic control register (read/write) ? offset d9h bit function type description 0 chip reset r/w chip and secondary bus re set. setting this bit will do a chip reset, without asserting s_rstout# and forcing secondary reset bit in bridge control register to be set. after resetting all bits except for the secondary reset bit in bridge control register, this bit will be cleared but not. write 0 has no effect. 2:1 test mode r/w reserved 3 secondary reset output mask r/w 1 = primary reset input p_rstin# active will not cause secondary reset output s_rstout# to become active. if this bit is set, p_rstin# will not reset primary port control logic state machines. power not good (pwrgd = 0) clears this bit to 0. 4 primary reset output mask r/w 1 = secondary reset input s_rsti n# active will not cause primary reset output p_rstout# to become active. power not good (pwrgd = 0) clears this bit to 0. 5 primary reset r/w forces the assertion of p_rstout# signal pin on the primary interface. reset to 0. 0=do not force the assertion of p_rstout# pin 1=force the assertion ?0? at p_rstout# pin secondary reset control bit is in bridge control register. 7:6 reserved r/o reserved (set to 0). arbiter control register (read/write) ? offset dah bit function type description 8-0 arbiter control r/w each bit controls whet her a secondary bus master is assigned to the high priority group or the low priority group. bits <8:0> correspond to request inputs s_req#[8:0], resp ectively. reset value is 0. 9 pci 6254 priority r/w defines whether the secondary port of pci 6254 is in high priority group or the low priority group 0=low priority group 1=high priority group. reset to 1. 15:10 reserved r/o reserved (set to ?0?s) 19.2.11 power mana gement registers power management register s deh, e0h and e3h are eeprom loadable or ror write enable loadable, but is read only during normal operation. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 176 this register is set to 01h to indicate power management interface registers. capability identifier (r/o) ? offset dch next item pointer (r/o) ? offset ddh set to e4h. this field provides an offset into the func tion's pci configuration space pointing to the location of next item in the function's capability list. in pc i 6254, this points to the hot swap registers. power management capabilities(r/w) ? offset deh bit function type description 0-2 version r/o this register is set to 001b, indicating that this function complies with rev 1.0 of the pci power management interface specification 3 pme clock r/o this bit is a '0', indicating that pci 6254 does not support pme# signaling 4 auxiliary power source r/o this bit is set to ?0? since pci 6254 does not support pme# signaling 5 dsi r/o device specific initialization. returns ?0? indicating that pci 6254 does not need special initialization 6-8 reserved r/o reserved 9 d1 support r/o returns ?1? indicating that pci 6254 supports the d1 device power state 10 d2 support r/o returns ?1? indicating that pci 6254 supports the d2 device power state 11-15 pme support r/o set to ?0601? in revi sion aa. set to ?7e01? in revision ab. power management control/ status(r/w) ? offset e0h bit function type description 0-1 power state r/w this 2-bit field is used bot h to determine the current power state of a function and to set the function into a new power state. the definition of the field values is given below. 00b - d0 01b - d1 10b - d2 11b ? d3hot 2-7 reserved r/o reserved 8 pme enable r/w this bit is set to ?0? since pci 6254 does not support pme# signaling. 9-12 data select r/o this field returns ?0000b? indicating pci 6254 does not return any dynamic data. 13-14 data scale r/o returns ?00b? when read. pci 6254 does not return any dynamic data. 15 pme status r/w this bit is set to ?0? si nce pci 6254 does not support pme# signaling. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 177 pmcsr bridge support(r/w) ? offset e2h bit function type description 0-5 reserved r/o reserved 6 b2/b3 support for d3hot r/o this bit reflects the state of t he bpcc input pin. a ?1? indicates that when pci 6254 is programmed to d3hot state the secondary bus?s clock is stopped. 7 bus power control enable r/o this bit reflects the state of the bpcc input pin. a ?1? indicates that the power management state of the seconda ry bus follows that of pci 6254 with one exception, d3hot state. power management data register (r/w) ? offset e3h this register is eeprom loadable or ror write enable lo adable, but is read only during normal operation. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 178 19.2.12 hot swap registers capability identifier (r/o) ? offset e4h this register is set to 06h to indicate hot swap interface registers. next item pointer (r/o) - offset e5h set to e8h. this field provides an offset in to the function's pci configuration space pointing to the location of next item in the function's capabilit y list. in pci 6254, this points to the vital product data (vpd) registers. hot swap register(r/w) ? offset e6h (for pci 6254 rev aa, register e6h can only be access ed from the primary port. in non-transparent mode and when the secondary port is connected to hot swap connector , in order to access this register, the host needs to establish handshake with the intelligent subsystem on the primary port to instruct the primary port subsystem to write this register) bit function type description 0 dha r/w device hiding arm. reset to 0. 1 = arm device hiding 0 = disarm device hiding dha is set to 1 by hardware during hot swap port pci rstin# going inactive and handle switch is still unlocked. the locking of the handle will clear this bit. 1 eim enum# mask status r/w enables or disables enum# assertion. reset to 0. 0 = enable enum# signal 1 = mask off enum# signal 2 pie r/o pending insert or extract: this bit is set when either ins or ext is ?1? or ins is armed (write 1 to ext bit). 1 = either an insertion or an extraction is in progress. 0 = neither is pending 3 loo led status r/w indicates if led is on or off. reset to 0. 0 = led is off 1 = led is on 5-4 pi r/w programming interface: hardcode at 01: ins, est, loo, eim and pie, device hiding are supported. 6 ext extraction state r/w1c this bit is set by hardware when the ejector handle is unlocked and ins = 0. 7 ins insertion state r/w1c this bit is set by hardwar e when hot swap port rstin# is deasserted, eeprom autoload is comp leted and the ejector handle is locked. writing 1 to ext bit also arms ins. 15:8 reserved r/o reserved and a read returns all 0. write has no effect. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 179 19.2.13 vpd registers capability identifier (r/o) - offset e8h this register is set to 03h to indicate vpd registers. next item pointer (r/o) - offset e9h set to 00h. vpd register (r/w) ? offset eah bit function type description 1-0 reserved r/o reserved 7-2 vpd address r/w vpd operation : writing a ?0? to this bit generates a read cycle from the eeprom at the vpd address specified in bits 7-2 of this register. this bit will remain at a logic ?0? value until eeprom cycle is finished, then it be set to ?1?. data for reads is available at register ech writing a ?1? to this bit generates a write cycle to the eeprom at the vpd address specified in bits 7-2 of th is register. this bit will remain at a logic ?1? value until eeprom cycle is finished, then it be cleared to ?0?. 14-8 reserved r/o reserved 15 vpd operation r/w vpd operation : writing a ?0? to this bit generates a read cycle from the eeprom at the vpd address specified in bits 7-2 of this register. this bit will remain at a logic ?0? value until eeprom cycle is finished, then it be set to ?1?. data for reads is available at register ech writing a ?1? to this bit generates a write cycle to the eeprom at the vpd address specified in bits 7-2 of th is register. this bit will remain at a logic ?1? value until eeprom cycle is finished, then it be cleared to ?0?. vpd data register (r/w) ? offset ech bit function type description 31-0 vpd data r/w vpd data (eeprom data[addr + 0x40]) - the least significant byte of this register corresponds to the byte of vpd at the address specified by the vpd address register. the data read from or written to this register uses the normal pci byte transfer capabilities. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 180 x x x x x x x 19.3 non-transparent mode operation pci 6254 can also operate as a non-transparent univ ersal bridge, which can be used for embedded type applications and for application on cpci system and perip heral slots. in this mode, pci 6254 uses up to 3 base address registers on each side of the bridge to spec ify which cycles are passed downstream or upstream, after being translated using the values in the address tr anslation registers. non-transparent mode is enabled through the trans# pin. pci 6254 has the following non-transparent capabilities: downstream address translation upstream address translation separate configuration space for primary and secondary interfaces up to three separate address ranges can be specifi ed by using standard base addr ess register definition support for 32-bit i/o, 32-bit memory and 64-bit memory address translation translation registers are all eeprom loadable, so pci 6254 can o perate in non-tr ansparent mode without special software requirements powerful message register mechanism, doorbells, st atus and events with interrupt capability to pass information from one side of the bridge to the other side. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 181 19.4 interrupts msi is a non-shared interrupt that enforces data consiste ncy. the system guarantees that any data written by the device prior to sending the msi has reached its final desti nation before the interrupt service routine accesses the data. msi enables pci 6254 to request service by writ ing a system-specified message to a system-specified address (pci dword memory write transaction). the tr ansaction address specifies the message destination and the transaction data specifies the message. syst em software initializes the message destination and message during device configuration. 19.4.1 direct message interrupts the pci 6254 has 4 upstream and 4 downstream me ssage registers which when written to, can generate immediate interrupts to the other side. this is the fastest interrupt mechanisms that pci 6254 has and is faster in latency than standard doorbell interrupts for software applications. 19.4.1.1 direct message interrupt operations when a pci master wants to communicate with the host on the other side of the pci 6254 bridge, it can make use any of the 4 message byte registers available. when the master writes an encoded message into this message register, the write action causes an interrupt be generated to the host. the interrupt service routine can first read the interrupt status registers to see wh ich message status bit has been set and read the message register to get the interrupt message. the service routine should then write 1 to the corresponding status bit to clear the status. this allows the service routine to react to the encoded message quickly without performing to many polling of registers. 19.4.2 doorbell interrupts the pci 6254 has 16 upstream and 16 downstream doorbe ll interrupt registers which when written to, can generate immediate interrupts to the other side. 19.4.2.1 doorbell interrupt operations when a pci master wants to communicate with the host on the other side of the pci 6254 bridge, it can make use any of the 16 doorbell interrupts. when the requesting master first writ es 1, then writes 0 to its doorbell interrupt request bit, an interrupt will automatically be generated to the host. t he interrupt service routine can read the doorbell status register to find out who is re questing the interrupt and can then go and inquire the corresponding device. the service routine should then write 1 to the corresponding status bit to clear the status. 19.4.3 message signaled interrupts (msi) msi is a non-shared interrupt that enforces data consiste ncy. the system guarantees that any data written by the device prior to sending the msi has reached its final desti nation before the interrupt service routine accesses the data. msi enables pci 6254 to request service by writ ing a system-specified message to a system-specified address (pci dword memory write transaction). the tr ansaction address specifies the message destination and the transaction data specifies the message. syst em software initializes the message destination and message during device configuration. interrupt latency (the time from interrupt signal ing to interrupt serving) is system dependent. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 182 x x x x x x 19.4.3.1 msi operation during configuration time, system software does the followings: scan the function?s capability list; the function implements msi (capability id of 05h exists). reads the msi capability structure?s message control register to determine the function?s capabilities. reads the multiple message capable field to determine the number of requested messages. writes the multiple message enable field to allocate either all or a subset of the requested messages. initializes the msi capability structure?s message ad dress register and messag e upper address register with a system-specified message destination address. initializes the msi capability structure?s message da ta register with a tw o bytes system-specified message (one word). once msi is enabled, the function may send messages using a dword memory write to the address specified by the contents of the message address register. the dword that is written is made up of the value in the message data register. if the multiple message enable fiel d is non-zero, pci 6254 can modify the low order bits of the message data to generate multiple messages. if the msi write transaction results in a data parity error, the master that originated the msi write transaction is required to assert serr# and set the appropriate bit in th e status register. the message receiver must complete the interrupt message transaction in dependent of when the cpu services the interrupt. if a device requires one interrupt message to be serviced before another, then the device must not send the second interrupt message until the first one has been serviced. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 183 19.5 non-transparent mode boot up sequence pci 6254 loads eeprom on power up and during this time any configuration cycle will end up with retry. depending on which port is set to have higher boot priority by the p_boot input, the lower priority boot master access to the pci standard bar registers will be retired unless xb_mem input is set to ?1?. access to other configuration register s are not affected. upon reset, the corresponding port portready status bit is cleared to indicate that the port is not yet ready for access by the controlling host. high priority boot master (in general is the intelligent subsystem) can allocate a memory and/or i/o region that can be accessed by the low boot priority host (in general , the system control host). after that, the high boot priority master should set it s corresponding portready bit. once this bit is set, the retried bar access configuration cycle from the low boot priority boot master can proceed and therefore the low boot priority boot master can proceed with normal pci initialization to set up the correct memory/io space allocation. there are semaphores that can be used to ensur e exclusive access to shared registers. there are multiple cross bridge interrupt mechanisms fo r use. direct interrupt mechanism allows user encode message to be written to registers that can cause interrupt s. it is up to the designer to decide on the definitions used in the message registers. there are also 16 door bell registers for user to use for cross bridge communications. port reset, port power-down can also be configured to cause interrupts for the opposite port to respond. note that all the address translation registers can be stored into the eeprom and then loaded during the eeprom autoload process, so that no software is r equired to setup the transl ation mechanism between the primary and secondary hosts. 19.5.1 using xb_mem input to avoid initial retry latency the portready mechanism, which results in retry for bar access configuration cycles if subsystem is not yet set up, can be disabled if the xb_mem input pin is c onnect to high. in such event, the pci 6254 hardcoded a fixed cross bridge communication window of 16mb memory space at power up. pci 6254 will automatically claim such 16m of memory space. this allows the boot up of the low priority boot port to move forward without waiting for the priority boot port to progr am the corresponding memory bar re gisters. when the xb_mem (prv_mem pin in transparent mode) pin is ?1?, the p or s po rt_ready mechanism will not be relevant and access to bar registers will not be retried. although the defaul t claims 16m, the bar registers can be changed by eeprom or software to change the window size. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 184 hb 6 aut ol oa ds tr an s l at i o n m a s k regi s t er s f r om e e p r o m i f a v ai l abl e prio r i t y bo ot m a s t e r init ili a z e s p r i o r i t y b oot i n t er f a c e conf i gur at i o n r egi s t er s p r og ra m s prio r i t y bo o t in t e rf ac e cr os s b r i dge c o m m uni c a t i on w i ndow s i ze by s e t t i n g tr an s l at i o n m a sk r e g i st e r s, pr ogr am s t r ans l a t i o n a ddr es s re gi s t er s se t s i t s por t r e a d y b r t e nabl e t r a n s l at i o n m app i n g i f c r os s br i d g e h ands hak e co mp le t e s po w e r up or pc i r e s e t p c i s t andar d b a r c o n f i g u r a t i on c y c l e s f r om l o w boo t pr i o r i t y m a s t e r a r e re t r ie d , all o t h e r c r o s s br i dge t r af f i c i s tar get a bor t e d pr io r i t y bo o t por t r e a d y bit s e t no lo w b o o t p r io ri ty m a s t e r i n it il ia z e s i t s ow n hb 6 i n t e r f a c e conf i gur at i o n r egi s t er s ye s p r ogr am l o w boo t pr i o r i t y i n t ef ac e tr ans l a t i o n a ddr es s re gi s t er s p r i or i t y b oot m a s t e r s ends m e s s a g e t o l o w bo ot pr i o r i t y m a st e r t o e s ta blis h c r o s s br i d g e i n t er f a c e h ands ha k i ng lo w boo t pr i o r i t y m a s t er s end s me ssa g e t o pr i o r i t y b o o t m a ste r t o es t abl i s h c r os s br i dge i n t e r f ac e han ds hak i n g e n abl e tr an s l at i o n m app i ng i f c r o s s br i d g e ha nds hak e com p l e t e s p r i or i t y b o ot m a s t er ( t y p i c al l y i n t el l i gent s ubs y s t em ) h b 6 i n te r f a c e in i t i a li z a ti o n low boot pr i o ri t y m a s t er ( t y p ica l ly co n t r o ll in g h o st ) h b 6 in t e rfac e i n it ia l i za ti o n 1 2 3 4 3 2 4 5 5 n otes: 1 . tr ans l a t i on m a s k r egi s t er va l u e s ar e re ad f r om e e p r o m o f f s et s 32h, 33 h, 3e h , 3 f h 2 . e x t ende d r egi s t er s at i n d e x e d ad dr es s 8h- a h f o r s e c ondar y por t , ch- e h f o r p r i m a r y por t . 3 . the p o r t _ r e a d y bi t s , at e x t ended r egi s t er s a t i nde x ed add re s s b h s e c ond ar y po rt a nd f h f o r p r i m ar y por t , a r e c l e a r ed upon p _ rs t i n_l a nd s _ rs ti n _ l . . 4 . h a n d s hak i n g c a n be ac hi eved us i ng d i re c t m e s s a ge i n t e r r u p t s at r e gi s t er a 4 h- a 8h. hand s h ak i n g m e s s ages ar e u s e r - d e f i ned s t at u s/ c o m m a nd i n f o r m at i o n . 5 . tr ans l a t i on c an be enabl ed at e x t end ed r e g i s t e rs at i n dex e d a ddr es s f h ( p r i m a r y ) and b h ( s e c o n dar y ) . pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 185 19.6 non-transparent application system configuration overview the followi ng are so me a s sumptio n s fo r this overview. 1. there is at le ast one p r o c e s sor on e a ch side of pci bus. 2. p_boot input is set to 1: p_port has hi gh er boot p r iorit y and need to finish ba sic b oot up setu p first. 3. primary re set and se co nda ry reset input s have be en applie d pro p e r ly. 4. eeprom aut o load sequence i s com p leted after pr im ary reset going inacti ve if eeprom is used. 5. eject han d le is clo s e d and hot swap p r o c ed ure h a s b een do ne if hot-plug a ppli c ation is ap plie d. p r o c essor pc i dev i ce pc i dev i ce pc i d e v i ce pc i d e v i ce hb 6 n on- t r anspaa r e n t mode proce ssor ch ip se t p r o c essor processor chi p s e t s_ p o r t s i d e p_p o rt sid e pc i bu s pci bus 19.6. 1 mem o ry allocation registers initialization the followi ng steps d e mon s trate the initi a lizatio n pro c edure of syst em software t o prog ram th e memory ma pping regi sters. since p_boot is set to ?1? in th is appli c ation note, s_port, the lower p r i o rity port, will be retri ed du ring config uratio n acce sses to its bar0, bar1 and bar2 c onfig uratio n regi sters. wh en prima r y port intelligent sub s ystem fin i she s its ba si c co nfiguratio n setup a nd set the p_port_re ady bit to ?1?, the retri e d config uratio n a c c e s s e s b y s_ po r t ma s t er c a n pr oc ee d. if the above mentione d ret r ies a r e n o t desirable, xb_ mem pi n inpu t can be u s ed to set a fixed 16mb cross bridg e comm uni cati on win d o w s i n bar0 0x10 h config uratio n regi ster in b o th side s up o n reset. this wind ows si ze can be changed by eeprom or software afterwar d. this would allow lo wer priority boot port to move forward without having to wait for the highe r prio rity port to set the co rresp ondi ng m e mory bar. programmin g to the resp ective up strea m addre ss t r an sla t ion regi sters and do wn stream address tran sl ation regi sters is required when address tra n slation mecha n ism is d e si re d. when xb_ me m pin is ?1 ?, the p_port_rea dy and s _ port_ready mech ani sm will not be rel e vant and co nfiguratio n acce sses to bar0, 1 and 2 will not be ret r ied. many cross b r idge relate d control re gist ers a r e lo ca te d in the extended re giste r s area a nd p r o g ramm ed through config uratio n regi ster 0x d3 h (extende d registe r index) and 0xd4 h (extended regi ster data port). pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 186 19.6.2 basic initialization sequence p_port side (high boot priority port): 1. program the desired cross bridge memory window si ze at extended register 0x0bh for bar0, bar1, and bar2. 2. if address translation is desired, program the a llocated memory location to the translation address registers at extended register 0x 08h, 0x09h and 0x0ah and enable the upstream translation enable bits in extended register 0x0bh. 3. set p_port_ready bit to ?1? in bit 31 of extended register 0x0fh. 4. check if s_port_ready bit is set to ?1? then go to step 3. otherwise, go back to step 2. (time-out mechanism, to prevent dead lock, can be implemen ted to safeguard against a faulty subsystem that never sets the s_port_ready.) 5. checks the desired total memory size from c onfiguration register 0x 10h, 0x14h and 0x18h and then initialize these registers accordingly per pci specific ation. now the memory access is established in the space specified by configurat ion register 0x10h, 0x14h, and 0x18h on the p_port side. 6. program the rest of configuration register s_port side (need to wait until high boot priority port is setup): 1. check p_port_ready bit. if it is set to ?1?, go to step 2. otherwise, go back to step 1. (time-out mechanism, to prevent dead lock, can be implemente d to safeguard against a f aulty system that never sets the p_port_ready.) 2. check the p_port assigned total cross bridge memo ry size from configuration register 0x10h, 0x14h and 0x18h and then initialize these registers accordingly per pci specification. 3. program the s_port allocated memory size to extended register 0x0fh for bar0, bar1, and bar2. 4. if address translation is desired, program the a llocated memory location to the translation address registers at extended register 0x 0ch, 0x0dh and 0x0eh and enable t he downstream translation enable bits in extended register 0x0fh. now the memory access is established in the space specified by configuration register 0x10h, 0x 14h, and 0x18h on the s_port side. 5. set s_port_ready bit to ?1? in bit 31 of extended re gister 0x0bh and program the rest of configuration registers. note that all the address translat ion registers can be stored into t he eeprom and loaded during the eeprom autoload process. if desired, no software is required to setup the translation mechanism between the primary and secondary hosts. if xb_mem input is not used, software se tting of p_port_ready or s_port_ready is required to enable access to bar registers by low boot priority port. to avoid overlap accesses by software, there are semaphore bits that can be used to ensure exclusive access to shared registers. please refer to the semaphore section in the pci 6254 data book. pci 6254 provides multiple cross bridge interrupt mechanisms for use. direct interrupt mechanism allows user encoded message to be written to registers that can caus e interrupts. it is up to the designer to decide on the definitions used in these message regi sters. there are also 16 doorbell registers to use for cross bridge communications. port reset, port power-down can also be configured to cause interrupts for the opposite port to respond. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 187 19.6.3 example of address setup and mapping the following diagram demonstrates the relationships of bar allocation register, address mask (region) and translation registers. please note that address translation is only available to higher order address bits. bar0 and bar2 translate only a31:a12 and bar1 only translates a31:a20 or a63:a20. for upstream memory access: 1. bit 8-15 of extended register 0x 0bh been programmed to 0x0001,0111b to set 8mb memory space for secondary configuration register bar1 0x14h. 2. upstream translation address register in extended register 0x0 9h been programmed to 0x2000,0000h to allocate the 8mb memory space from location 0x2000,000 to 0x207f,ffffh in primary side of memory space. 3. 0x14h bar1 register in secondary configur ation register been programmed to 0x0a00,0000h. 4. any memory access between location 0x0a00,0000h to 0x0a7f,ffffh to pci bus in secondary side of memory space is transferred to access location 0x20 00,0000h to 0x207f,ffffh in primary side of memory space. for downstream memory access: 1. bit 8-15 of extended register 0x0fh been progra mmed to 0x1001,1000b to set 16mb memory space for primary configuration register bar1 0x14h. bit 15 =1 to indicate the memory space is prefetchable. 2. downstream translation address register in ext ended register 0x0dh been programmed to 0x5000,0000h to allocate the 16mb memory space from location 0x 5000,000 to 0x50ff,ffffh in secondary side of memory space. 3. 0x14h bar1 register in primary configurat ion register been programmed to 0x3000,0000h. 4. any memory access between location 0x3000,0000h to 0x30ff,ffffh to pci bus in primary side of memory space is transferred to access location 0x5000,0000h to 0x50ff,ffffh in secondary side of memory space. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 188 pr imar y c o nf igur at ion r e gi st er 0 x 08h bar 0 tr an sl a t i o n ad d r es s 0 x 09h 0 x 2 000 ,00 00h bar 1 tr an sl a t i o n ad d r es s 0x0a h bar 2 tr an sl a t i o n ad d r es s upstream o ffset val u e 0 x 10h 0 x 14h 0 x 3 000 ,00 00h 0 x 18h i/o o r memor y b a r 0 mem o ry ba r 1 mem o ry ba r 2 p r imary side memor y map o ffset va lue 0x 10 h 0x 14 h 0x0a 00,0 0 0 0 h 0x 18 h i/o o r memor y b a r 0 memo ry ba r 1 memo ry ba r 2 secondar y configur ation regi ster 0x 0a08 ,0 00 0h 0x 30 2a,00 0 0 h 0x 0 c h bar 0 t r an sl a t i o n ad d r es s 0x 0 d h 0x5 000 ,00 00h bar 1 t r an sl a t i o n ad d r es s 0x0e h bar 2 t r an sl a t i o n ad d r es s downst ream bi t 7 -0 ba r 0 a ddres s ma sk bi t 15-8 10 01, 1 000b ba r 1 a ddres s ma sk bi t23 - 16 ba r 2 a ddres s ma sk down st rea m , 0x0 f h bi t 7 -0 bar 0 add r e ss m a sk bi t 15-8 0 001, 0 111b bar 1 add r e ss m a sk b i t 2 3-16 bar 2 add r e ss m a sk up trea m , 0x0bh ex t e nded conf igu r a t ion regist er, 0xd3 ( o ff set) , 0xd4 (data) s econdary side m e mory m a p 0x 0000 , 000 0h 0 x fff f,ff ff h 0x 0a08 , 0 0 00h 0x 502 a, 00 00h 0x0 000, 0 000h 0 x f fff ,fff fh 0x 2008 , 000 0h 0 x 3 02a, 0 000 h 0x 5000 , 000 0h 0x50 ff , f ff f h 0x 2000 , 000 0h 0x2 07f , f f f f h 0 x 0 a 7 f ,ffffh 0x 0a00 , 0 0 00h 0x30 00, 00 00h 0x30 ff , f ff fh pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 189 20 ieee 1149.1 compatible jtag controller an ieee 1149.1 compatible test access port (tap) cont roller and the associated t ap pins are provided for board level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst#. all digital input, output, input/output pins are te sted except the tap pins and clock pin. the ieee 1149.1 test logic consists of a tap controller, an instruction register, and a group of test data registers including bypass, device identification and boundary sc an registers. the tap controller is a synchronous 16 state machine driven by the test cl ock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the machine is in reset state at power-up. pci 6254 implements 3 basic instructio ns: bypass, sample/preload, and extest. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 190 21 eeprom important: wrong eeprom data can cause the pci 6254 to lock the system. designers should provide an optional switch to disable the eeprom in their board design. pci 6254 has an interface to eeprom device. the interfac e can control an issi is24c 02 or compatible part, which is organized as 256x8 bits. the eeprom is used to initialize the registers. after p_rstin# is deasserted, pci 6254 will automatically load data from the eeprom. the data structure is defined in the following section. the eeprom interface is organized on 16-bit base in little-endian fo rmat, and pci 6254 supplies a 7-bit eeprom word address. the following pins are used for the eeprom interface: x eepclk: eeprom clock output x eepdata: eeprom bi-directional serial data pin x ee_en#: low input enabl es eeprom access. note: the pci 6254 does not control the eeprom address inputs. it can only access eeprom with address inputs set to 0. 21.1 auto mode eeprom access using auto mode, pci 6254 can acce ss the eeprom on a word basis via hardware sequence r. users need only to access a word data via pci 6254 configuration registers fo r eeprom start control, address, read/write command. before each access, software should check the auto mode cycle in progress status before issuing the next start. 21.2 eeprom mode at reset upon p_rstin# going high, pci 6254 auto-loads input for eeprom automatic load condition if input pin ee_en_l = 0. (in rev aa in non-transparent mode, eeprom load is triggered by pwrgd going active instead) the first offset in the eeprom contains a signature. if the signature is recognized, register auto-load will commence right after reset. duri ng the auto-load, pci 6254 will read se quential words from the eeprom and write to the appropriate registers. before the pci 6254 registers can be accessed through host, user should check the auto-load condition by reading the eepauto bit. host access is allowed only after eepauto status becomes '0' which means that the auto load initialization sequence is complete. 21.3 pci 6254 rev aa only: eeprom auto load in non-transparent mode in non-transparent mode and upon pw rgd rising edge, the pci 6254 initia tes eeprom autoload. however for registers that are also reset by p_rstin#, includi ng vendor id and subvendor id, the autoload will not be effective if p_rstin# is active. therefore in order to have effective autoload, the pwrgd rising edge should be aligned with the rising edge of p_rstin#. it is also important to note that the eeprom initialized value will be cleared by any active p_rstin# or power management initiated internal reset. only another pwrgd rising edge or a software initiated chip reset (register d9h, bit 0) will cause eeprom load again. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 191 21.4 eeprom data structure followi ng the reset, if the condition abov e is met, pci 6254 will auto-load the regi sters with dat a from eeprom. the following table desc r ibes t he data s t ruc t ure us ed in eeprom. the pci 6254 accesses the eeprom one word at a time. it is important to note that in the data phase, bit orders are reverse o f that of the a ddre s s pha se . pci 6254 on ly suppo rts e eprom device add r e ss 0. a c k m s b m s b l s b l s b s t o p data (n) d ata (n +1) a c k a c k wo r d a ddre ss (n) m s b l s b 0 s t a r t 10 a c k w r i t e dev i ce a ddre s s 10 0 00 10 a c k a c k wo r d a ddre ss (n) m s b l s b w r i t e dev i ce a ddre s s 0 10 0 00 s t a r t 10 a c k r e a d de v i ce a ddres s 10 0 00 a c k m s b m s b l s b l s b da t a (n) d ata (n + 1 ) n o a c k s t o p s t a r t read: wr ite : pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 192 21.4.1 eeprom address and corresponding pci 6254 register eeprom byte address pci configuration offset description 00-01h eeprom signature: autoload will only proceed if it reads a value of 1516h on the first word loaded. 0x1516=valid signature, otherwise disable autoloading. 02h region enable: enables or disables certain regions of the pci configuration space from being loaded from the eeprom. valid combinations are: bit 0: reserved bits 4-1: 0000 = stop autoload at offset 03h: group 1 0001 = stop autoload at offset 13h: group 2 0011 = stop autoload at offset 23h: group 3 0111 = stop autoload at offset 27h: group 4 1111 = autolo ad all eeprom loadable registers: group 5 other combinations are undefined. bits7-5: reserved 03h enable miscellaneous functions: bit0: isa enable control bit write protect : when this bit is set, pci 6254 will change the standard pci-to-pci bridge control register 3eh bit 2 into read only and isa enable feature will not be available. bit1-7: reserved end of group 1 04-05h 00-01h vendor id 06-07h 02-03h transparent device id in rev aa, eeprom loaded non-transparent device id bit 0 is not inverted. 08h reserved 09h 09h transparent mode class code : contains low byte of class code register 0ah-0bh 0ah-0bh transparent mode class code higher bytes : contains, upper bytes of class code register 0ch 0eh transparent header type 0dh 09h non transparent mode class code : contains low byte of class code register 0eh-0fh 0ah-0bh non transparent mode class code higher bytes : contains, upper bytes of class code register 10h 0eh non transparent header type 11h 0fh bist 12h-13h 50h internal arbiter control end of group 2 14h 44h primary flow through control 15h 45h timeout control 16h-17h 46-47h miscellaneous options 18h 48h primary initial prefetch count 19h 49h secondary initial prefetch count 1ah 4ah primary incremental prefetch count 1bh 4bh secondary incremental prefetch count 1ch 4ch primary maximum prefetch count 1dh 4dh secondary maximum prefetch count 1eh 4eh secondary flow through control 1fh e3h power management data pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 193 20h-21h e0h power management csr 22h- 23h deh power management capabilities end of group 3 24h-25h 2ch subsystem vendor id , 2ch(non-transparent mode) 26h-27h 2eh subsystem id , 2eh(non-transparent mode) end of group 4 28h reserved 29h bit 0-2: upstream address translation enable bit 3: upstream bar 0 i/o bit bit 7-4: bits 15-12 of upstream bar 0 translation address 2ah-2bh bits 31-16 of upstream bar 0 translation address 2ch bit0: upstream bar 0 prefetchable bit bit1: upstream bar 1 64 bit bit2: upstream bar 2 prefetchable bit bit3: upstream bar 1 prefetchable bit bit 7-4: bits 23-20 of upstream bar 1 translation address 2dh bits 31-24 of upstream bar 1 translation address 2eh-2fh bits 15:0 of upstream bar 2 translation address 30h-31h bits 31:16 of upstream bar 2 translation address 32h-33h bits 4-0: upstream bar 0 translation mask bits 10-5: upstream bar 1 translation mask bits 15-11: upstream bar 2 translation mask 34h reserved 35h bit 0-2: downstream address translation enable bit 3: downstream bar 0 i/o bit bit 7-4: bits 15-12 of downstream bar 0 translation address 36h-37h bits 31-16 of downstream bar 0 translation address 38h bit 7-4: bits 23-20 of downstream bar 1 translation address bit0: downstream bar 0 prefetchable bit bit1: downstream bar 1 prefetchable bit bit2: downstream bar 2 prefetchable bit bit3: downstream bar 1 64 bit 39h bits 31-24 of downstream bar 1 translation address 3ah-3bh bits 15:0 of downstream bar 2 translation address 3ch-3dh bits 31:16 of downstream bar 2 translation address 3eh-3fh bits 4-0: downstream bar 0 translation mask bits 10-5: downstream bar 1 translation mask bits 15-11: downstream bar 2 translation mask pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 194 22 vital product data x x vpd related registers are located starting at offset ech of the pci configuration space. x pci 6254 contains the vital product data (vpd) registers as specified in the pci local bus specification revision 2.2. the vpd information is stored in the eeprom device along with the autoload information. pci 6254 provides for storage of 192 byte s of vpd data in the eeprom device. vpd also uses the enhanced capabilities port address mechanism. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 195 x x support for d0, d3 management states x x support of the b2 secondary bus power state when in the d3 anagement state next state 23 pci power management pci 6254 incorporates functionality that meets the requi rements of the pci power management specification, revision 1.0. these features include: pci power management registers using the enha nced capabilities port (e cp) address mechanism hot and d3 cold power support for d0, d1, d2, d3 hot and d3 cold power management states for devices behind the bridge hot power m table 23-1 below shows the states and related acti ons that the pci 6254 performs during power management transitions. (no other transactions are permitted.) table 23-1: states and related actions during power management transitions current state action d0 d3 cold power has been removed from the pci 6254. a power-up reset must be performed to bring the pci 6254 to d0. d0 d3 hot if enabled to do so by the bpcce pin, the pci 6254 will disable the secondary clocks and drive them low. d0 d2 unimplemented power state. the pci 6254 will ignore the write to the power state bits (power state remains at d0). d0 d1 unimplemented power state. the pci 6254 will ignore the write to the power state bits (power state remains at d0). d3 hot d0 the pci 6254 enables secondary clock outputs and performs an internal chip reset. signal s_rstout# will not be asserted. all registers will be returned to the reset values and buffers will be cleared. d3 hot d3 cold power has been removed from the pci 6254. a power-up reset must be performed to bring the pci 6254 to d0. d3 cold d0 power-up reset. the pci 6254 performs the standard power-up reset functions. 23.1 p_pme# and s_pme# signals. in transparent mode, s_pme# is passed through to p_pm e#. the use is optional as some designers can choose to connect pme# signal directly from secondary pci devices to the primary port. in non-transparent mode, depending on the setting of p_boot, pme# will be passed from the high boot priority port to the low boot priority port. the pass through mechanism can be enabled/disabled via the power management control register. . pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 196 24 hot swap pci 6254 in corpo r ate s function ality that meets the r equi reme nts of the co mpactp ci hot swap sp e c ificatio n picmg 2.1 r2.0 with high availability programmi ng i n terfac e level 1 (pi = 1). the compac tp ci hot swap regi ster block is lo cated at pci configu r atio n offset e4h. desig ners sho u ld refe r to the compactp ci hot swap spe c ification for detaile d im plementatio n guidelin e . im portan t n o te : if hot-s w a p fea t ure is no t need ed, l_ stat and e j ect inpu ts must be co nnec t ed to logic ?0 ?. other w i s e the pci 62 54 ma y not function. enum # can be left unconn ecte d . 24.1 early power support pci 6254 in corpo r ate ea rl y power sup port in the followin g way s : x pci 625 4 ca n tolerate b a c k en d inte rface bein g u n powere d whe n fully po we red by ea rly powe r. pci 6 254 three - state s a ll pci signal s of a port until its co rre sp on ding rsti n# is dea sserte d . x whe n fully po wered by b a ck en d po we r, pci 6254 th ree-st ates all pci sign als o f a port until it s corre s po ndi ng rstin# i s de as serte d . ea r l y po we r p o w e r g ood p _ r e s e t# , s _ r e s e t # ej e c t pc i b u s buf f e r s in t r i - s t a t e p_clk& s _ c l k ye s no r m a l pci bu s st a t e e j ec t - h a n d l e o p en e j ec t - h a n d l e c l os e d i n act i ve a c t i ve power n o t g o o d p o w e r g ood no po w e r po we r on h b 6- a b h o t - i n ser t i o n p o w e r u p s e q u e n ce r eco m m en d a t i o n 24.2 assignment of hot swap port in no n unive r sal mo de, th e prima r y po rt is hot s w a p c apa ble. in unive r sal m ode, se con d a ry port i s hot plug cap able. all hot swap rel a ted co ntrol will be a ssi gn ed to the co rresp ondi ng hot swap ca pa ble port. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 197 x enum#: this is the output signal enum# to notify the system host that eit her a board has been freshly inserted or is about to be extracted. enum# is an op en collector signal. enum# is asserted if ins or ext bit is set and eim is 0. 24.3 hot swap signals pci 6254 has the following hot swap related pins: x l_stat: this is the status blue led. led is illuminated if rstin# is asserted. led is also illuminated when the loo bit is asserted and rstin# is deasserted. led is an active high signal that allows other circuit to drive the blue led. x eject: this is the handle switching input. this si gnal should be debounced by external hardware and must be connected to logic ?0? if hot swap function is not used. this signal can cause the assertion of enum#. gpio pins designated for recommended hot swap use: x healthy# (gpio7): this can be used as the boar d healthy health# output. this pin has internal weak pull-up. subsystem software can set the pin to output the desired board healthy status to the system and to control the custom logic generated hot swap port rstin#. 24.4 hot swap register control and status pci 6254 hot swap register is located at e6h. 24.5 avoiding initially retry or in itially not responding requirement the portready mechanism, which results in retry for bar access configuration cycles if subsystem is not yet set up, can be disabled if the xb_mem input pin is c onnect to high. in such event, the pci 6254 hardcoded a fixed cross bridge communication window of 16mb memory space at power up. pci 6254 will automatically claim such 16m of memory space. this allows the boot up of the low priority boot port to move forward without waiting for the priority boot port to progr am the corresponding memory bar re gisters. when the xb_mem (prv_mem pin in transparent mode) pin is ?1?, the p or s po rt_ready mechanism will not be relevant and access to bar registers will not be retried. although the defaul t claims 16m, the bar registers can be changed by eeprom or software to change the window size during reset, the pci 6254 is a not responding device. therefore designer can use gpio7, for example, to generate healthy# control by the subsystem to cont rol the local_pci_rst# input to the pci 6254 hot swap port. pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 198 pci 6254 implements device hiding to eliminate mid-transaction extractions. when device hiding is invoked, pci 6254 shall term inate current configurati on transaction by signaling disconnect. following the completion of the current transaction (which is disconnected), pci 6254 shall not respond as a target to any subsequent tr ansactions until device hiding is canceled. 24.6 device hiding pci 6254 invokes device hiding by hardware upon hot swap after rstin# becomes inactive and ejector handle is still unlocked. pci 6254 will be quiesced by software before device hiding is invoked. current trans action will be completed as early as possible. pci 6254 will not initiate a transacti on as a master and will not respond as a target to io transactions and will not signal interrupts. if pci 6254 is not participating in a transaction when de vice hiding is invoked, pci 6254 shall not respond as a target to any subsequent transactions until device hiding is canceled. device hiding is cancelled when the handle switch is relocked. 24.7 implementing hot swap cont roller using pci 6254 gpio pins in transparent mode, gpio[15-8], which have weak internal pull-low, can be used for connection to radial signals bd_sel#. gpio[7:0], which have weak internal pull-up, can be used for radial signals healthy#. enum# can be used to trigger health inquiry by reading the gpio ports. pci 6254 d a ta bo o k v 2 .1 2003 plx technology , inc. a ll rights reser v e d. 199 this specification outlines the me chanical dimensions for pci 6254. 25 packag e s p ecif i cations 0 e e2 e3 e1 e b a2 a a1 c pin a01 c o rner pin a01 c o rner pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 200 the following table lists the package dimensions in millimeters. tolerance is 0.05mm unless otherwise specified dimension symbol min nom max a overall package height 2.53 2.13 2.33 a1 package standoff height 0.50 0.60 0.70 a2 encapsulation thickness 1.12 1.17 1.22 b ball diameter 0.60 0.75 0.90 c substrate thickness 0.51 0.56 0.61 e ball pitch 1.27 e overall package width 30.80 31.00 31.20 e1 27.94 e2 overall encapsulation width 28.8 29.00 29.20 e3 25.00 pci 6254 data book v2.1 2003 plx technology, inc. all rights reserved. 201 (above which the useful life may be impair ed. for user guidelines, not tested). 26 electrical specifications 26.1 maximum ratings parameter minimum maximum storage temperature range -55 c 125 c junction temperature 125 c supply voltage, v dd 3.9v maximum voltage to signal pins 5.5v maximum power 2.0w note: stresses greater than those listed under maxi mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions above those indicated in the opera tional sections of this specifica tion is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. 26.2 functional operating range parameter minimum maximum supply voltage 3.0 v 3.6 v operating ambient temperature 0 c 70 c 26.3 dc electrical characteristics symbol parameter condition min max unit notes v dd supply voltage 3.0 3.6 v v io pvio, svio pin interface i/o voltage 3.0 5.5 v v ih input high voltage 0.5 v dd v io v v il input low voltage -0.5 0.3 v dd v v p a 0.1 ol output low voltage i iout = 1500 v dd v v oh output high voltage i iout = -500 p a 0.9 v dd v i il input leakage current 0 < v in < v dd 2 p a c in input pin capacitance 7.0 pf pci 6254 d a ta bo o k v 2 .1 ? 2003 plx technology , inc. a ll rights reser v e d. 202 26.4 pci signal timing specification 26.4. 1 pci si gnal timing s y mb o l p a r a me t e r m i n i mu m m a x i mu m u n i t t val clk to signal valid delay - bused signals 2 8 n s t val( ptp) clk to signal valid delay ? point to point 2 8 n s t on float to active delay 2 - ns t off active to float delay - 14 ns t su input setup tim e to clk ? bused signals 3 - n s t su(ptp) input setup tim e to clk ? point to point 5 - t h input signal hold tim e from clk 0 . 5 - n s |
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